Differential delay line clock generator with feedback phase cont

Details Differential delay line clock generator with feedback phase cont Differential delay line clock generator with feedback phase cont

1996-05-10

1998-10-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327141, 327153, 327161, 377 47, G06F 108

Patent

active

058282505

ABSTRACT:
An on-chip clock waveform generator for generating from an externally supplied clock (EFI) an on-chip (internal) clock with a 50% duty cycle having a clock rate of 1/2, 1, or 2 times that of EFI, is based on a tapped delay line with a tap-to-tap differential delay of approximately 1% of the external clock (EFI) period. The waveform generator detects the tap at which a full period of delay occurs between delay line input and the tap. By knowing the tap for a first full period delay the generator determines the taps at which the 1/4, 1/2, and 3/4 period waveform states can be observed. The pulses corresponding to fractional periods, are used to generate standard pulse width streams that correspond to 1/4 period intervals. A programmed multiplexer/selector selects the proper sequence from these pulse streams to drive an RS flip-flop in order to produce the output 50% duty-cycle clock running at 1/2, 1, or 2 times the external (EFI) clock. Generally, the system can produce output clocks with 50% duty cycle and with rates greater than, equal to, or less than the external clock (EFI). Other optional operating modes generate 25% duty cycle waveforms at 1/2 the rate of EFI. A feedback signal is generated by comparing the phase of the generated on-chip clock with the phase of EFI which is used to adjust the overall delay of the generator in order to improve synchronism between EFI and the on-chip clock.

REFERENCES:
patent: 4266197 (1981-05-01), Breithaupt
patent: 4675612 (1987-06-01), Adams et al.
patent: 4700347 (1987-10-01), Rettberg et al.
patent: 4789996 (1988-12-01), Butcher
patent: 4870665 (1989-09-01), Vaughn
patent: 4999526 (1991-03-01), Dudley
patent: 5022056 (1991-06-01), Henderson et al.
patent: 5022057 (1991-06-01), Nishi et al.
patent: 5097489 (1992-03-01), Tucci
patent: 5101117 (1992-03-01), Johnson et al.
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5146478 (1992-09-01), Dragotin
patent: 5148113 (1992-09-01), Wight et al.
patent: 5191234 (1993-03-01), Murakami et al.
patent: 5223755 (1993-06-01), Richley
patent: 5260608 (1993-11-01), Marbot
patent: 5281874 (1994-01-01), Sorrells et al.
patent: 5317202 (1994-05-01), Waizman
patent: 5363406 (1994-11-01), Han
patent: 5374860 (1994-12-01), Llewellyn
patent: 5438254 (1995-08-01), Ho et al.

Affiliated with

Also associated with

Rating

Differential delay line clock generator with feedback phase cont does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Differential delay line clock generator with feedback phase cont, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Differential delay line clock generator with feedback phase cont will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1616348