Differential delay line clock generator

Details Differential delay line clock generator Differential delay line clock generator

1994-09-06

1996-07-16

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

327116, 327118, 327175, 377 47, G06F 108

Patent

active

055370683

ABSTRACT:
An on-chip clock waveform generator for generating from an externally supplied clock (EFI) an on-chip (internal) clock with a 50% duty cycle having a clock rate of 1/2, 1, or 2 times that of EFI, is based on a tapped delay line with a tap-to-tap differential delay of approximately 1% of the external clock (EFI) period. The waveform generator detects the tap at which a full period of delay occurs between delay line input and the tap. By knowing the tap for a first full period delay the generator determines the taps at which the 1/4, 1/2, and 3/4 period waveform states can be observed. The pulses corresponding to fractional periods, are used to generate standard pulse width streams that correspond to 1/4 period intervals. A programmed multiplexer/selector selects the proper sequence from these pulse streams to drive an RS flip-flop in order to produce the output 50% duty-cycle clock running at 1/2, 1, or 2 times the external (EFI) clock. Other optional operating modes generate 25% duty cycle waveforms at 1/2 the rate of EFI. Because the generator is a feed-forward network, settling times are shorter than prior art methods using feedback loops (e.g., phase-locked loops).

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