Differential delay cell having controllable amplitude output

Details Differential delay cell having controllable amplitude output Differential delay cell having controllable amplitude output

2006-10-24

2006-10-24

Mis, David (Department: 2817)

Oscillators

Ring oscillators

C327S246000

Reexamination Certificate

active

07126431

ABSTRACT:
A differential delay cell includes a current source for establishing an operating current and a differentially coupled transistor pair having a common node, two input nodes, and two output nodes. The common node is coupled to the current source, and the two output nodes are coupled to an impedance load. The impedance load establishes a time delay between each of the input nodes and a corresponding one of the output nodes. Differential output signals are generated at said two output nodes in response to input signals coupled to said two input nodes. An amplitude control device is coupled between the two output nodes for controlling an amplitude of the differential output signals being generated.

REFERENCES:
patent: 5638030 (1997-06-01), Du
Johns, David and Ken Martin.Analog Integrated Circuit Design.Published by John Wiley and Sons, Inc.: New York, 1997, pp. 1-2.
Maneatis, John G. “Low-Jitter Process-Independent DLL and PLL Based on Self-BiasedTechniques”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.

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