Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-03-29
2001-09-18
Wong, Peter S. (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
C323S312000
Reexamination Certificate
active
06291977
ABSTRACT:
FIELD OF INVENTION
The invention relates to a current mirror, and in particular, to the differential current mirror having low or eliminated output differential current offset.
BACKGROUND OF THE INVENTION
A typical current mirror circuitry
10
, which can be found in textbooks on microelectronics, is shown in
FIG. 1
a
(see, e.g. “Microelectronics Circuits” by Adel S. Sedra and Kenneth C. Smith, Oxford University Press, 1991, pp. 428-435). This current mirror is known to be sensitive to parasitic resistances caused by interconnections between a transistor and other circuit elements as illustrated by dotted boxes in FIG. la at interconnection points “a”, “b”, “c” and “d”. It means that minor variations of parasitic resistances result in exponential changes of the output current, which might be unacceptable in many practical situations. As an improvement to
FIG. 1
a
, another prior art current mirror circuit
20
, shown in
FIG. 1
b
, includes regeneration resistors R
1i
, R
1o
, R
2i
, and R
2o
at corresponding interconnection points. As a result, the improved current mirror becomes substantially less sensitive to parasitic resistances due to the fact that regeneration resistances are much greater than parasitic resistances and therefore provide much less relative variations of the magnitude of the combined resistances.
However, introduction of regeneration resistors, while solving the above-mentioned circuit sensitivity problem, introduces another inherent problem of having a differential current offset caused by a mismatched layout of regeneration resistors. It means that the output differential current offset exists even though all the transistors are matched and differential current at the input of the current mirror is zero. Accordingly, there is a need to design a current mirror circuitry which would provide reduced or no differential current offset while maintaining other qualities of the circuitry.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a differential current mirror with low or eliminated differential current offset while providing low sensitivity to parasitic resistances at interconnection points.
According to one aspect of the invention there is provided a differential current mirror, comprising:
first and second input transistors Q
1i
and Q
2i
whose physical layout is being matched and emitters connected together to a first reference voltage V
ref1
through an input resistance means R
i
;
first and second output transistors Q
1o
and Q
2o
whose physical layout is being matched and emitters connected together to a second reference voltage V
ref2
through an output resistance means R
o
;
collector and base of the first (second) input transistor Q
1i
(Q
2
i) being connected to the base of the first (second) output transistor Q
1o
(Q
2o
) and to a first (second) input current terminal to which a first (second) input current i
1i
(i
2i
) is being supplied;
collector of the first (second) output transistor Q
1o
(Q
2o
) being connected to a first (second) output current terminal generating first (second) output current i
1o
(i
2o
).
Conveniently, it may be arranged that V
ref1
=V
ref2
=V
ref
and at least one of the input and output resistance means comprises a resistor. Alternatively, at least one of the input and output resistance means may comprise a semiconductor device having a resistance. Yet alternatively the input and output resistance means may comprise a variable resistance which is controlled by a digital or analog signal. Advantageously, it is provided that the magnitude of the variable resistance is a pre-determined function of the external signal, e.g. linear, quadratic, logarithmic or any other required function.
While preferred embodiments of the invention are illustrated for the current mirror based on BJT transistors, it is understood that other embodiments may include differential current mirrors using other transistors, e.g. MOSFET, FET, hetero-junction or any other known types of transistors.
Conveniently, a differential current gain of the current mirror may be controlled by changing magnitude of input and output resistances R
i
and R
o
and/or sizes of the transistors.
The differential current mirror of the invention is less sensitive to the parasitic resistances at interconnections and provides low or eliminated differential output current offset.
REFERENCES:
patent: 4583037 (1986-04-01), Sooch
patent: 4618815 (1986-10-01), Swanson
patent: 5371476 (1994-12-01), Nishioka
patent: 5436594 (1995-07-01), Pace et al.
patent: 5517143 (1996-05-01), Gross
patent: 5929678 (1999-07-01), Kaserkovitz et al.
patent: 5966050 (1999-10-01), Yoshino et al.
patent: 5977760 (1999-11-01), Kimura
patent: 6060956 (2000-05-01), Mole et al.
patent: 6081131 (2000-06-01), Ishii
patent: 6087819 (2000-07-01), Kuroda
Sedra, A.S., et al, “Microelectronic Circuits”, 3rdEdition, Oxford University Press, 1991, pp. 428-435.
Donnelly Victoria
Nortel Networks Limited
Vu Bao Q.
Wong Peter S.
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