Amplifiers – With semiconductor amplifying device – Including differential amplifier
Patent
1991-06-04
1992-07-21
LaRoche, Eugene R.
Amplifiers
With semiconductor amplifying device
Including differential amplifier
330257, 330261, H03F 345
Patent
active
051326400
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a differential current amplifier circuit formed in a semiconductor integrated circuit.
BACKGROUND ART
A conventional differential current amplifier circuit, which is designed to amplify a differential input current, has the structure illustrated in FIG. 1. More specifically, the circuit comprises a first signal input terminal IN1 and NPN transistors Q1 and Q2. The terminal IN1 is connected to receive an input signal current (I+i) consisting of a DC component I and a signal component (+i) superposed on the DC component. The collector-base path of the NPN transistor Q1 is connected to the first signal input terminal IN1 and the emitter of the NPN transistor Q1 is connected to the ground potential GND. The NPN transistor Q2 has an emitter area n times greater than that of the transistor Q1 and is connected to transistor Q2 in currentmirror fashion. The collector of the NPN transistor Q2 is connected to a first terminal OUT1. The transistors Q1 and Q2 form a first current mirror circuit. A second signal input terminal IN2 is connected to receive an input signal current (I-i) consisting of a DC component I and a signal component (-i) which is differential to the signal component (+i) and superposed on the DC component I. The amplifier circuit further comprises NPN transistors Q3 and Q4. The collector-base path of the NPN transistor Q3 is connected to the second signal input terminal IN2, and the emitter of the NPN transistor Q3 is connected to the ground potential GND. The transistor Q4 has an emitter area n times greater than that of the transistor Q3, and is connected to the transistor Q3 in current-mirror fashion. The collector of the transistor Q4 is connected to a second output terminal OUT2. The transistors Q3 and Q4 form a second current mirror circuit.
In the differential current amplifier circuit of FIG. 1, the collector current of the transistor Q2 (i.e., the current output from the first output terminal OUT1 is n(I+i), whereas the collector current of the transistor Q4 (i.e., the current output from the second output terminal OUT2) is n(I-i).
Therefore, the current gain Gi is: ratio of the emitter area of the transistor Q2 to that of the transistor Q1 or the ratio of the emitter area of the transistor Q4 to that of the transistor Q3.
FIG. 2 shows a modification of the differential current amplifier circuit of FIG. 1. This amplifier circuit is different from the circuit of FIG. 1 in that it has an input-signal current source and transistors Q5 and Q6. The current source supplies a differential input-signal current consisting of a DC component I and a signal component (either +i or -i) superposed on the DC component I. Since the circuit is identical to the circuit of FIG. 1 in all other respects, the same symbols and numerals are used to designate the same components as those illustrated in FIG. 1. The input-signal current source comprises PNP transistors Q01 and Q02 and a constant current source 60. The NPN transistors Q01 and Q02 have their emitters connected together and, thus, constitute a differential pair. The constant current source 60 is connected between the emitter node of the transistors Q01 and Q02 and a Vcc-current potential, and supplies a constant current 2I. The collectors of the transistors Q01 and Q02 are connected to the collectors of the transistors Q1 and Q3, respectively. Hence, when input voltages INA and INB, either containing a differential signal component, are applied to the bases of the transistors Q01 and Q02, signal currents (I +i) and (I-i) flow to the transistors Q1 and Q3, respectively. The PNP transistors Q5 and Q6 are connected together in mirror-current fashion. Their emitters are coupled to the Vcc potential, their bases are connected to each other, and their collectors are connected to the collectors of the transistors Q2 and Q4. The base and collector of the transistor Q6 are connected together. The collector of the transistor Q5 is coupled to an output terminal OUT. A load resistor RL is connected between the o
REFERENCES:
patent: 4238738 (1980-12-01), Komori
patent: 4451800 (1984-05-01), Nishioka et al.
patent: 4558287 (1985-12-01), Tanaka
patent: 4590435 (1986-05-01), Tanaka
patent: 4620161 (1986-10-01), Tanaka et al.
Kubo Makoto
Tanaka Tatsuo
Dinh Tan
Kabushiki Kaisha Toshiba
LaRoche Eugene R.
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