Differential control topology for LC VCO

Details Differential control topology for LC VCO Differential control topology for LC VCO

2000-05-18

2001-09-18

Grimm, Siegfried H. (Department: 2817)

Oscillators

Solid state active element oscillator

Transistors

C331S03600C, C331S17700V

Reexamination Certificate

active

06292065

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the electronic arts, and more particularly relates to a voltage controlled oscillator suitable for phase locked loop circuits such as may be employed in a high speed data communication link.
2. Brief Description of the Prior Art
Phase locked loops are important in the field of high speed data communication. They are employed in clock multiplier circuits, in which one or more high frequency output clocks are synthesized from a reference input. They are also used in clock and data recovery (CDR) circuits, in which the clock and data are recovered from a single high-speed serial stream of non-return to zero (NRZ) data. In systems which employ phase locked loop (PLL) circuits, the precision of the generated or recovered clock is critical to the performance of the system. Noise sensitivity of the components of the PLL can limit the quality of the generated or recovered clock, and may thus limit system performance. Clock multiplier circuits are used in conjunction with CDR circuits in local area networks, long-haul backbone networks, and/or wide area networks. Ethernet, Fibre Channel, and SONET/SDH) transmission systems are specific examples of systems which rely on PLL-based CDR circuits and clock multipliers. Furthermore, clock multiplier circuits are frequently found in microprocessors (where they are employed to generate the on-chip clock) and in radio frequency (RF) wireless communication systems (where they are used to synthesize carrier frequencies as needed).
A key component of a PLL is the oscillator. In a typical PLL, a voltage controlled oscillator (VCO) is phase locked to an input signal. The VCO oscillation frequency is set by the control voltage input to the VCO. The action of the PLL adjusts the control voltage, thus changing the VCO oscillation frequency, as the attempt is made to achieve phase lock. A number of different oscillator topologies are used in PLLs, but three of the most common are multivibrators, ring VCOs, and LC VCOs. Inductive-capacitive (LC) VCOs are often preferred over other topologies because of the superior phase noise performance and frequency stability which they exhibit. In an LC VCO, the control input acts to modify the capacitance in the LC portion of the circuit. Because the oscillator frequency is proportional to the inverse square root of the product of L and C, changing the capacitance in the LC circuit changes the VCO oscillation frequency. The control input acts on a circuit element that has a voltage-dependent capacitance. Commonly, this circuit element can be a varactor, but any circuit element having a voltage-dependent capacitance can be employed.
In many PLL applications, and particularly in data communications PLL applications, noise is an extremely important design concern. For a PLL, noise is typically quantified by measuring the jitter of the PLL output. Noise which couples into any part of the PLL will degrade the jitter performance of the loop, so low-noise design techniques are an integral part of virtually any PLL design. One such design technique involves making the signal path through the PLL differential, in order to suppress common mode noise. In the case of LC VCO-based PLL designs, however, the VCO control itself is typically implemented as single-ended.
In the prior art, there have been several LC VCOs designed for PLLs with pseudo-differential control inputs. One such LC VCO is discussed in the article by Gutierrez et al. entitled “2.488 Gb/s Silicon Bipolar Clock and Data Recovery IC for SONET (OC-48),” as archived in the proceedings of the IEEE Custom Integrated Circuits Conference at pages 575-578. In the approach of Gutierrez et al., the VCO control does not affect the LC tank itself, but instead modifies the current of emitter followers which are placed in the LC VCO's feedback circuit. This effectively adds an active delay stage to the LC VCO, thus degrading the circuit's low-noise properties. A second approach is described in an article by Nguyen and Meyer entitled “A 1.8-GHz Monolithic LC Voltage-Controlled Oscillator,” as published in the IEEE Journal of Solid-State Circuits, Volume 27, Number 3, in March 1992 at pages 444-450. In the approach of Nguyen and Meyer, two LC circuit outputs are mixed, in much the way as a delay interpolating ring VCO frequency is adjusted. In order for this approach to be fully differential, 4 LC circuits are effectively required, two LC circuits were used in the pseudo-differential approach as described in the Nguyen and Meyer paper.
The prior art approaches described to date do not implement full differential control. Furthermore, they do not properly treat the biasing of the voltage dependent capacitive elements which are used to set the VCO operating frequency.
In view of the foregoing, there is a need in the prior art for an LC VCO in which full differential control is implemented. Furthermore, there is the need for such an LC VCO which properly treats the biasing of the voltage dependent capacitive elements which are used to set the VCO operating frequency.
SUMMARY OF THE INVENTION
The present invention, which addresses the needs identified in the prior art, provides an LC VCO having an LC oscillator module with first and second tank nodes and a control module with positive and negative input voltage terminals. The control module includes first, second, third and fourth voltage dependent capacitive elements (VDCEs) each having a positive and a negative VDCE terminal. Each VDCE is configured to be biased for operation as a voltage-dependent variable capacitance.
The positive terminal of the first VDCE is coupled to the negative input voltage terminal, while one of the positive and negative terminals of the first VDCE is capacitively coupled to the second tank node. The positive terminal of the second VDCE is coupled to the negative input voltage terminal, while one of the positive and negative terminals of the second VDCE is capacitively coupled to the first tank node. The negative terminal of the third VDCE is coupled to the positive input voltage terminal, and one of the positive and negative terminals of the third VDCE is capacitively coupled to the second tank node. The negative terminal of the fourth VDCE is coupled to the positive input voltage terminal, and one of the positive and negative terminals of the fourth VDCF is capacitively coupled to the first tank node.
A diffrential voltage applied across the positive and negative input voltage terminals is operable to change capacitive properties of the VDCEs, so as to vary the output frequency of the LC oscillator module. Any effect on the output frequency of a common mode voltage applied to the positive and negative input voltage terminals tends to cancel.
In a preferred embodiment, the VDCEs are varactor diodes which are resistively biased. In other embodiments, the VDCEs can be, for example, field effect transistors (FETs), having a gate which functions as one terminal and a drain and source which are shorted together to function as another terminal.
These and other features and advantages of the present invention will be appreciated by reading the following specification, taken in conjunction with the accompanying drawings, and the scope of the invention will be set forth in the appended claims.


REFERENCES:
patent: 5422603 (1995-06-01), Soyuer
patent: 5434545 (1995-07-01), Burchfield
patent: 5781048 (1998-07-01), Nakao et al.
Li Lin et al., “A 1.4GHz Differential Low-Noise CMOS Frequency Synthesizer Using a Wideband PLL Architecture” 2000 IEEE SSCC Session 12/Frequency Synthesizers & Dividers/Paper TP 12.5 pp. 204-205 Feb. 8, 2000.
Nguyen et al., “A 1.8-GHzMonolithic LC Voltage-Controlled Oscillator”, IEEE Journal of Solid State Circuits, vol. 27, #3,3/92 pp. 444-450.
Gutierrez et al., “2.488 Gb/s Silicon Bipolar Clock and Data Recovery IC for Sonet (OC-48)” IEEE 1998 Custom Integrated Circuits Conference, AMCC, San Diego, CA pp. 575-578.

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