Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-11-06
2002-08-06
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S071000
Reexamination Certificate
active
06429695
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a differential comparison circuit for comparing differential signals.
2. Description of the Related Art
A comparison circuit for comparing differential signals has been used at present for a pipeline system A/D converter, for example. This pipeline system A/D converter is constituted by cascading a plurality of sample-and-hold circuits and acquires each bit value of the least significant bit (LSB)from the most significant bit (MSB) of pulse code modulation (PCM) data from comparison circuits arranged at their junctions. More concretely, the pipeline system A/D converter has the construction shown in
FIG. 4. A
sample-and-hold circuit SH is composed of a completely differential type operational amplifier
41
, and a plurality of these circuits SH is cascaded. In other words, output terminals out
1
and out
2
of a sample-and-hold circuit SH of a preceding stage are connected to input terminals in
1
and in
2
of a sample-and-hold circuit SH of a subsequent stage. The completely differential type operational amplifier
41
generates the differential signals from the output terminals outl and out
2
. These signals are output signals Voutl and Vout
2
that are the analog signals inverted mutually with a voltage equilibrium point V
1
of both output terminals as the center as shown in FIG.
5
. The voltage equilibrium point V
1
is accomplished by arranging feedback circuits having the same phase, not shown in the drawing, at the output terminals outl and out
2
and by adjusting the output bias of the completely differential type operational amplifier
41
.
Each comparison circuit
42
is disposed at the junction between the sample-and-hold circuit SH of a preceding stage and the sample-and-hold circuit SH of a subsequent stage. A comparator
52
of the comparison circuit
42
compares the output voltage of the sample-and-hold circuit SH of the preceding stage with a predetermined reference voltage equal to the voltage equilibrium point V
1
, or the voltages at output terminals out
1
and out
2
of the sample-and-hold circuit of the preceding stage with each other, to thereby judge “1” and “0” and outputs the result from the output terminal CO. When this judgment value is “1”, the sample-and-hold circuit SH of the subsequent stage outputs the voltage value that is twice the difference obtained by subtracting the voltage value corresponding to the judgment value “1” from the output voltage of the sample-and-hold circuit SH of the preceding stage. When the judgment value is “0”, the sample-and-hold circuit SH of the subsequent stage outputs the voltage value that is twice the difference obtained by subtracting the voltage value corresponding to the judgment value “0” from the output voltage of the sample-and-hold circuit SH of the preceding stage. Such a sample-and-hold operation is conducted as switching of a plurality of capacitances, not shown, connected to switch capacitance networks CS
1
and CS
2
and reset switches RS
1
and RS
2
interposed between the output terminals outl and out
2
and the input terminals in
1
and in
2
of the sample-and-hold circuit SH is effected. When such comparison operation and sample-and-hold operation are conducted, the analog signals are applied to the sample-and-hold circuit SH of the initial stage, and the comparison circuits
42
from the initial to last stages output each bit value of LSB from MSB of the PCM data, respectively. Each comparison circuit
42
includes an input amplitude monitor unit for monitoring whether or not the input signal of the sample-and-hold circuit SH is within a suitable allowable input range, in addition to a comparator
52
for conducting the comparison operation described above. The sample-and-hold circuit SH transmits therein the analog signals to the input terminals in
1
and in
2
through the switch capacitance networks CS
1
and CS
2
to the differential input terminals of the completely differential type operational amplifier
41
. Therefore, the suitable input range is determined by the differential amplitude rather than by the absolute value. The prior art technology expresses the predetermined amplitude value by use of the absolute value of the reference voltage as will be explained below.
In the comparison circuit
42
,the input amplitude monitor unit comprises comparators
43
,
44
,
47
and
48
, inverters
45
and
49
, AND gates
46
and
50
and an OR gate
51
. The comparator
43
compares the output signal Voutl with the reference voltage Vrefl (=1.5 V). The comparator
44
compares the output signal Vout
2
with the reference voltage Vref
2
(=0.5 V). The comparator
47
compares the output signal Voutl with the reference voltage Vref
2
. The comparator
48
compares the output signal Vout
2
with the reference voltage Vrefl. The output from the comparator
43
is given to one of the terminals of the AND gate
46
. The output from the comparator
44
is given to the other terminal of the AND gate
46
through the inverter
45
. When the output signals Vout
1
and Vout
2
are above 1.5 V and below 0.5 V, respectively, the comparator
43
outputs the logic level “1”, the comparator
44
outputs the logic level “0” and the AND gate
46
outputs the logic level “1”. Similarly, when the output signals Vout
1
and Vout
2
are below 0.5 V and above 1.5 V, respectively, the AND gate
50
outputs the logic level “1”. Therefore, the OR gate
51
in this embodiment output the logic level “1” notifying the excess of the allowable input range from the output terminal OVER when the amplitude difference between the output signals Vout
1
and Vout
2
is greater than 1 V.
However, the comparison circuit
42
shown in
FIG. 4
cannot make the most of the advantage of the differential signals created by the output signals Vout
1
and Vout
2
. For example, fluctuation of the power source voltage and of the voltage equilibrium point V
1
does not greatly affect the difference of the amplitude values of the output signals Vout
1
and Vout
2
, but the output signals Vout
1
and Vout
2
per se are greatly affected by such fluctuation. Since the comparison circuit
42
compares these output signals Vout
1
and Vout
2
as the discrete voltages with the predetermined reference voltages Vref
1
and Vref
2
, the comparison result is likely to be affected by the fluctuation of the power source voltage and the voltage equilibrium point V
1
. When the voltage equilibrium point vl shown in
FIG.5
shifts up or down, for example, the erroneous operation develops in any of the comparators
43
,
44
,
47
and
48
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a differential comparison circuit capable of easily acquiring desired circuit accuracy and capable of comparing differential signals with smaller influences of fluctuation of a power source voltage and a voltage equilibrium point.
A differential comparison circuit according to the present invention comprises a first MOS transistor using its gate terminal as a first input terminal and its source terminal as a second input terminal; a second MOS transistor having the same conduction type as that of the first MOS transistor, and using its gate terminal as a third input terminal and its source terminal as a fourth input terminal; a latch circuit having its first input/output terminal connected to a drain terminal of the first MOS transistor and its second input/output terminal connected to a drain terminal of the second MOS transistor; and a bias circuit for bringing the first and second MOS transistor into the same bias condition; wherein the difference of the input signals supplied to the first and second input terminals is compared with the difference of the input signals supplied to the third and fourth input terminals, and a comparison result is outputted from the first and second input/output terminals.
Preferably, the bias circuit described above includes a first current source connected between the source terminal of the first MOS tran
Miyabe Satoru
Sugimoto Yasuhiro
Jordan and Hamburg LLP
Nippon Precision Circuits Inc.
Tran Toan
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