Differential comparator with a programmable voltage offset...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

Reexamination Certificate

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Details

C372S062000, C372S074000, C324S537000, C324S555000

Reexamination Certificate

active

06323694

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an automatic tester. More particularly, the present invention relates to a differential comparator circuitry used to measure the timing properties of a device under test.
BACKGROUND
Test equipment is typically used to determine whether a device under test (“DUT”) follows a set of timing specifications. Accordingly, timing accuracy plays a vital role in the design of test equipment because a discrepancy in the timing accuracy can result in an incorrect classification of a DUT. For example, in some testing environments, provided a DUT follows a set of predetermined timing specifications, the DUT is categorized as a valid device for sale. Typically to pass as a valid device, each pin of a given DUT must satisfy timing requirements such as valid time, hold time, and setup time. These timing requirements, however, are susceptible to both electrical noise and transmission noise.
To counteract the effect of noise, conventional testers add a guardband to timing measurements. The timing guardband ensures that pin timings are not a product of noise. One disadvantage of adding a guardband is that it results in the testing equipment failing valid devices. In particular, the guardband makes the timing specification more stringent, thus DUTs that pass the timing specification but fail the guardband requirements are classified as failing devices.
FIG. 1A
illustrates a prior art testing device. In particular, test circuit
100
comprises two single-ended comparators (
120
and
130
) coupled to pin
110
. Using the single-ended comparator, test circuit
100
determines pin
110
's voltage transitions across a given threshold(s). As illustrated in
FIG. 1A
, each comparator is coupled to a different reference voltage. Comparator
120
is coupled to a high reference voltage CH
125
. Similarly, comparator
130
is coupled to a low voltage CL
135
. Accordingly, test circuit
100
determines whether pin
110
has crossed a high reference voltage or a low voltage.
Pin
110
's transition across the high voltage reference is indicated on output
140
. Similarly, pin
110
's transition across the low voltage reference in indicated on output
150
. For one embodiment, pin
110
is the output of a DUT. Accordingly, output
140
and output
150
indicate a logic high output and a logic low output, respectively.
FIG. 1B
illustrates the timing of pin
110
. In particular, the horizontal axis of timing chart
105
shows time (“t”). The vertical axis of timing chart
105
shows the voltage level of pin
110
. The vertical axis of timing chart
105
also shows the voltage level of reference voltages CH
125
and voltage CL
135
. The reference voltage levels CH
125
and CL
135
are used to determine logic low and logic high outputs, respectively. Accordingly, test circuit
100
recognizes pin
110
as a logic low for t<151 and t>158. Test circuit
100
also recognizes pin
110
as a logic high for 152<t<156.
Test circuit
100
, however, is susceptible to noise. Test circuit
100
is susceptible to noise because the reference voltages CH
125
and CL
135
remain stable. On the other hand, the signal generated by pin
110
is affected by electrical noise and transmission reflections. Accordingly, the comparison of pin
110
to the steady reference values is skewed. For example, at time
157
, noise creates a negative voltage shift on pin
110
. The negative voltage shift delays the high to low transition of pin
110
. Thus, a tester that excepts a logic low value on pin
110
prior to time
158
will incorrectly determine that the DUT does not follow timing specifications.
To counteract the effects of noise, some DUTs include differential outputs. Differential outputs are used because a voltage measurement based on the difference in the value between a pair of differential outputs is less susceptible to electrical noise and transmission line reflections. Conventional testers, however, have disadvantages when used in conjunction with differential outputs.
One disadvantage of using a conventional tester with differential outputs results when a common mode component exists in the differential output. Typically, a common-mode component offsets the signal transitions of a pair of differential outputs. The offset, however, corrupts the output of a single-ended comparator used in conventional testers. The corruption occurs because the single-ended comparator compares a single output versus a reference voltage. Accordingly, the single-ended comparator is unable to distinguish offset signal transitions that are readily apparent when compared against the signal transition of a related differential output.
To counteract the disadvantage of using a single-ended comparator, some prior art testers use a differential comparator. In particular, the differential comparator is coupled to a pair of differential outputs. One disadvantage of using a differential comparator results from the design characteristics of the differential comparator. In particular, a differential comparator determines whether a pair of signals is equal in value. Accordingly, if one of the differential outputs is erroneously held at a direct current (“DC”) value while the other output transitions normally, the tester is unaware of the DC error. The tester is unaware of the DC error because the tester detects intervals where the DC output and the transitory signal intersect, thus the tester incorrectly assumes that both differential outputs are transitioning properly. Another disadvantage of using a differential comparator results from the introduction of capacitive coupling. In particular, when a pair of tester channels are used as inputs for a differential comparator, the differential comparator creates capacitive coupling between the channels. Capacitive coupling results in electrical and/or transmission noise between the channels, thus reducing timing accuracy in the tester circuit.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a voltage offsettable differential comparator for use in test equipment.
A testing circuit is disclosed. The testing circuit is configured to examine a differential output of a device under test. The testing circuit includes an offsettable differential comparator coupled to the differential output of the device under test. The offsettable differential comparator generates a digital signal corresponding to a voltage difference on the differential output.
Other objects, features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.


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Gillette, Garry C.,A Single Board Test System: Changing the Test Paradigm, IEEE (1995), Paper 37.2, pp. 880-885.
Garry C. Gillette, A Single Board Test System: Changing The Test Paradigm, International Test Conference, IEEE 1995, pp. 880-885.
Will Creek, Characterization of Edge Placement Accuracy in High-Speed Digital Pin Electronics, International Test Conference Proceed

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