Differential/coherent digital demodulator operating at multiple

Demodulators – Frequency shift keying or minimum shift keying demodulator

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329304, 329341, 375324, 375362, H04L 2714, H04L 2722

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active

054402654

ABSTRACT:
Symbols (18) of a burst (12) are sub-divided into symbol sections (20). Each symbol section (20) is sampled and converted into polar coordinates. A buffer bank (38) selectably delays the samples and replays a preamble (14). A demod bank (40) includes a coherent demod (58) and several differential demods (60). Each differential demod (60) processes its own stream of symbol sections (20). The differential demods (60) feed a preamble detector (66) and a symbol synchronization circuit (62). The symbol synchronization circuit (62) identifies the symbol section (20) which yields the smallest magnitude of frequency errors. This symbol section (20) is processed by the coherent demod (58) to acquire carrier phase and recover data. The coherent demod (58) is implemented in the phase domain so that only oscillation signal phase data need be generated in phase locked loops. Two phase locked loops (110, 112) operate in parallel but with initial reference phase offsets so that at least one of the two loops will not experience hang-up.

REFERENCES:
patent: 4491805 (1985-01-01), Laures et al.
patent: 4856027 (1989-08-01), Nakamura et al.
patent: 5097220 (1992-03-01), Shimakata et al.
patent: 5377232 (1994-12-01), Davidov et al.
Stanford Telecommunications, Inc., ASIC & Custom Products Short Form Catalog, Aug. 1993, pp 1 through 8.
Alberty et al., "A New Pattern Jitter Free Frequency Error Detector", IEEE Transactions On Communications, vol. 37, No. 2, Feb. 1989, pp. 159-163.

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