Differential clock signals encoded with data

Details Differential clock signals encoded with data Differential clock signals encoded with data

2006-03-28

2006-03-28

Burd, Kevin (Department: 2631)

Pulse or digital communications

Pulse code modulation

Differential

C375S242000, C375S354000, C375S357000, C375S376000

Reexamination Certificate

active

07020208

ABSTRACT:
The number of pins on an integrated circuit chip is reduced by encoding control signals into a differential clock. The differential clock has two clock lines with complementary signals that together represent a clock. Control signals inside a clock-transmitting chip are input to an encoder which determines which control signal is being asserted or de-asserted. The encoder drives a clock-control signal that either forces both differential clock lines low or stops the differential clock from pulsing. A clock-receiving chip detects the both-low or stopped differential clock and determines which control signal was asserted or de-asserted. A phase-locked loop (PLL) in the receiver keeps an internal clock running even when the differential clock is missing pulses. A sequence of M1 missing clock pulses, followed by N1 clock pulses, followed by M2 missing pulses encodes the control signal, where M1, N1, and M2 are whole numbers.

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