Differential circuit with controllable offset

Details Differential circuit with controllable offset Differential circuit with controllable offset

1987-04-24

1988-06-28

LaRoche, Eugene R.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

330253, H03K 522, H03F 345

Patent

active

047541695

ABSTRACT:
In various analog applications, it is desirable to have a known offset voltage at the input of a comparator, operational amplifier, or other type of differential stage. For example, in an ISDN receiver, the use of a desired offset allows for discriminating between signals having different amplitudes. In the present technique, a reference current, derived from a reference voltage (V.sub.ref) and on-chip resistor (R1) is used to set the currents through two input transistors, typically MOS transistors. An offset resistor (R0) in the source lead of one of the transistors produces a voltage drop that sets the offset at an input of the differential stage. The voltage drop across R0 is proportional to (V.sub.ref .times.R0)/R1. Since R0 and R1 are fabricated by the same process, their ratio is independent of temperature, process, etc. Therefore, a well-defined offset is obtained.

REFERENCES:
patent: 4464631 (1984-08-01), Prentice

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