Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2003-04-18
2004-05-25
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S095000, C327S066000
Reexamination Certificate
active
06741105
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2002-126214, filed on Apr. 26, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a peak hold circuit which detects and outputs the peak value of an input voltage.
Recently, there are growing demands for a lower supply voltage and lower power consumption for semiconductor devices that are used in various electronic devices. This necessitates that a peak hold circuit which is mounted on a semiconductor device should secure a fast and stable hold operation in addition to reduction in the supply voltage and power consumption.
FIG. 1
is a circuit diagram of a conventional peak hold circuit
50
. The emitters of PNP transistors Tr
1
and Tr
2
are connected to a current source
1
which operates in accordance with the supply of a supply voltage Vcc. An input voltage Vin is supplied to the base of the transistor Tr
1
whose collector is supplied to the collector of an NPN transistor Tr
3
and the base of an NPN transistor Tr
5
. The emitter of the transistor Tr
3
is connected to ground GND.
The collector of the transistor Tr
2
is connected to the collector of an NPN transistor Tr
4
and the bases of the transistors Tr
3
and Tr
4
and the emitter of the transistor Tr
4
is connected to the ground GND. The transistors Tr
3
and Tr
4
form a current mirror circuit.
The base of the transistor Tr
2
is connected to the collector of the transistor Tr
5
and an output terminal To and the emitter of the transistor Tr
5
is connected to the ground GND.
The output terminal To is connected to one end of a hold capacitor
2
whose other end is connected to the ground GND. The output terminal To is connected to a voltage supply (Vcc) via a reset switch
3
.
In the peak hold circuit
50
, with the supply voltage Vcc supplied, and the reset switch
3
is switched on, the hold capacitor
2
is charged and an output voltage Vout output from the output terminal To is reset to the supply voltage Vcc. As the reset switch
3
is switched on every predetermined time, the hold capacitor
2
is charged and the output voltage Vout output is reset to the supply voltage Vcc.
Next, the reset switch
3
is switched off, causing the input voltage Vin to be supplied to the base of the transistor Tr
1
. When the input voltage Vin is lower than the supply voltage Vcc, the collector current of the transistor Tr
1
increases. As the collector currents of the transistors Tr
3
and Tr
4
do not increase, however, the collector current of the transistor Tr
5
increases, causing the hold capacitor
2
to be discharged.
As the output voltage Vout falls and becomes equal to the input voltage Vin, the collector currents of the transistors Tr
1
and Tr
2
become equal to each other. As a result, the transistor Tr
5
is turned off, stopping the discharging of the hold capacitor
2
.
When the input voltage Vin becomes higher than the output voltage Vout, the collector current of the transistor Tr
1
decreases, thereby keeping the transistor Tr
5
switched off. Therefore, the output voltage Vout does not fall and the input voltage Vin is held.
The peak hold circuit
50
should improve the response speed of the output voltage Vout with respect to the input voltage Vin. This requires that a bias current I
B
which is supplied to the transistors Tr
1
and Tr
2
from the current source
1
should be increased to increase the collector currents of the transistors Tr
1
and Tr
2
.
That is, in a case where the input voltage Vin becomes higher than the output voltage Vout after the output voltage Vout is held at the minimum voltage, the transistor Tr
5
should be turned off promptly to stop the discharging of the hold capacitor
2
. This requires that the base current of the transistor Tr
5
should be absorbed quickly by the collector current of the transistor Tr
3
which operates according to the collector current of the transistor Tr
2
. To improve the accuracy of the hold voltage, therefore, it is necessary to increase the bias current I
B
supplied from the current source
1
.
If the collector current (bias current I
B
) of the transistor Tr
2
is increased, however, the base current of the transistor Tr
2
increases, so that the base current flows into the hold capacitor
2
at the time of the hold operation. This brings about the shortcoming that the output voltage Vout rises gradually, thus lowering the accuracy of the peak hold voltage.
Changing the transistors Tr
1
and Tr
2
to P channel MOS transistors can overcome the problem of the reduced accuracy of the hold voltage. However, the threshold value of MOS transistors is about 1 V, which is greater than the base-emitter voltage V
BE
of bipolar transistors. The output voltage Vout is therefore held so long as it is lower by at least 1 V than the supply voltage Vcc. The use of PMOS transistors therefore makes it difficult to cope with the reduction in supply voltage Vcc.
PMOS transistors vary considerably and the amplification factor of the PMOS transistors is smaller than that of bipolar transistors. This makes the control of the transistor Tr
5
unstable, which may lead to lower accuracy of the output voltage Vout. Further, the coexistence of bipolar transistors and PMOS transistors complicates the fabrication process.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a differential circuit receives first and second input voltages. The differential circuit includes a first input transistor for receiving the first voltage. A second input transistor is connected to the first input transistor to receive the second input voltage. A current source is connected to the first and second input transistors to supply bias current to the first and second input transistors. A bypass circuit is connected to the first and second input transistors and the current source, for bypassing the bias current to suppress an increase in collector current of the first input transistor or the second input transistor based on the first and second input voltages.
A further aspect of the present invention is a peak hold circuit for receiving an input voltage and making a hold voltage. The peak hold circuit includes a first input transistor having a base for receiving an input voltage. A second input transistor is connected to the first input transistor and has a base to receive the hold voltage. A current mirror circuit is connected to the first and second input transistors to supply identical collector current to the first and second input transistors. A hold capacitor is connected to the second input transistor to supply the hold voltage to the second input transistor. A reset switch is connected to the hold capacitor to reset the hold voltage. A hold-voltage setting transistor is connected to the hold capacitor and the first and second input transistors to receive base current from the collector of the first input transistor and make the hold voltage coincide with the input voltage in accordance with the base current. A bypass circuit is connected to the second input transistor, for bypassing bias current to be supplied to the second input transistor when the hold-voltage setting transistor is turned off.
A further aspect of the present invention is a peak hold circuit for receiving an input voltage and making a hold voltage. The peak hold circuit includes a first differential circuit including a first input transistor having a base for receiving the input voltage and a collector, a second input transistor connected to the first input transistor and having a base for receiving the hold voltage, and a first current mirror circuit, connected to the first and second input transistors, for supplying a same collector current to the first and second input transistors. A hold capacitor is connected to the second input transistor to supply the hold voltage to the second input transistor. A reset switch is connected to the hold capacitor to reset the hold voltage. A ho
Shimizu Katsuya
Watabe Ayuko
Yasukouchi Katsuyuki
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