Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-09-04
2001-04-24
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S536000
Reexamination Certificate
active
06222402
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electronic clock circuits, and more particularly to an electronic clock that is particularly suited for a high-speed microprocessor, which uses a phase-lock loop (PLL) circuit having an improved charge-pump that reduces or eliminates transient currents in complementary metal-oxide semiconducting (CMOS) switching devices, thereby providing a more linear response for small phase errors.
2. Description of Related Art
Electronic circuits that provide clock signals are used in a wide assortment of devices, and particularly in computer systems. Microprocessors and other computer components, such as random access memory (RAM), device controllers and adapters, use clock signals to synchronize various high-speed operations. These computer clock circuits often use a phase-lock loop (PLL) circuit to synchronize (de-skew) an internal logic control clock with respect to an external system clock.
A typical prior art PLL circuit
1
is shown in FIG.
1
and includes a phase/frequency detector (PFD)
2
, a charge-pump
3
, a low-pass filter
4
, and a voltage-controlled oscillator (VCO)
5
. Phase/frequency detector
2
compares two input signals, a reference signal f
ref
(from the external system clock) and a feedback signal f
fb
, and generates phase error signals that are a measure of the phase difference between f
ref
and f
fb
. The phase error signals (“UP” and “DOWN”) from detector
2
are used to generate control signals by charge-pump
3
which are filtered by low-pass filter
4
and fed into the control input of voltage-controlled oscillator
5
. Voltage-controlled oscillator
5
generates a periodic signal with a frequency which is controlled by the filtered phase error signal.
The output of voltage-controlled oscillator
5
is coupled to the input f
fb
of phase/frequency detector
2
directly or indirectly through other circuit elements such as dividers
6
, buffers (not shown) or clock distribution networks (not shown), thereby forming a feedback loop. If the frequency of the feedback signal is not equal to the frequency of the reference signal, the filtered phase error signal causes the frequency of voltage-controlled oscillator
5
to shift (upwards or downwards) toward the frequency of the reference signal, until voltage-controlled oscillator
5
finally locks onto the frequency of the reference; following frequency acquisition, phase acquisition is achieved in a similar manner. The output of voltage-controlled oscillator
5
is then used as the synchronized signal (for internal logic control). In cases where the incoming data is a self-clocking bit stream, the comparator system is used to extract the clock information from the data stream itself.
One problem with phase/frequency detectors is that jitter is introduced into the loop due to the “dead zone.” The phase error signal that controls the VCO has a first polarity in the case where the reference signal has a phase lag, and the other polarity when a phase lead is detected. For very small phase differences (e.g., the zero-phase-error, steady-state condition of the locked PLL), in the transition from one polarity to the other there is often a region referred to as the dead zone where the phase error signal is insensitive to phase-difference changes. However, it is important that the control characteristic of the PLL be linear in a phase-difference interval that contains the zero-phase-error point, in order to avoid the VCO uncontrollably changing its phase. In this dead zone (or dead band) the VCO's eventual output signal is unpredictable and liable to dither.
High-performance, low-jitter PLL's thus require accurate sensing and correction of the phase and frequency error between the reference and feedback clock signals. A plot of this control voltage as a function of phase error should produce a linear response over the cycle and should pass through the origin (dead zone), as shown by the dashed line in FIG.
2
. The actual response of conventional devices, however, is discontinuous (bent), primarily as a result of certain transient currents which are highly variable.
These troublesome transient currents can be understood by considering how conventional charge-pumps have current sources and sinks which are gated by complementary metal-oxide semiconducting (CMOS) devices switched by the PFD outputs. The gated devices are in series with the current sources and sinks (which may or may not be programmable for controlling the magnitude of the current). The gated devices may be at the top and bottom of the stack as seen in
FIG. 3
of “A Wide-Bandwidth Low-Voltage PLL for PowerPC™ Microprocessors,” IEEE Journal of Solid-State Circuits, vol. SC-30, pp. 383-391 (April 1995). The gated devices can also be within the stack, as shown in FIG.
3
. In such structures, the switching device forces the current in the current sources/sinks to be shut off, resulting in large biasing differences between conducting and non-conducting states.
In the circuit of
FIG. 3
for example, node pm
1
will rise to the level of the supplied analog voltage AV
dd
when the input UPB from the PFD is high (the unasserted state). When UPB is asserted (low), the initial current in device Ip
2
is larger than the desired peak current (normally supplied by Ip
1
) since the source-to-gate voltage V
sg
is approximately equal to AV
dd
, and parasitic capacitances on node pm
1
contribute additional transient currents. For small phase errors, the charge-pump's response is dominated by the initial transient current (phase errors corresponding to the region between the origin and points ax or bx on FIG.
2
), generating a higher slope region at the origin and a discontinuity in the response after the transient has died out (discontinuities “A” and “B”). The transient current is not well-controlled since it is due to parasitics and will be different for charge and discharge operations, creating a discontinuity in the slope at the origin of the transfer function (discontinuity “C”).
In light of the foregoing, it would be desirable to devise an improved charge-pump which eliminated or substantially reduced these transient currents. It would be further advantageous if the transients could be effectively eliminated over the full range of current settings, in a charge-pump having programmable current sources and sinks.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved clock circuit, such as may be used with a microprocessor or other high-performance computer components.
It is another object of the present invention to provide such a clock circuit having a phase-lock loop (PLL) which uses a charge-pump and filter to supply differential control inputs to a voltage-controlled oscillator.
It is yet another object of the present invention to provide a clock circuit using such a charge-pump which reduces or eliminates transient currents in switching devices to yield a more linear response for small phase errors.
The foregoing objects are achieved in a charge-pump circuit generally comprising a first error signal input, a second error signal input, a control signal output, first means for switching the control signal output to a current source in response to a first error signal received at the first error signal input, second means for switching the control signal output to a current sink in response to a second error signal received at the second error signal input, and means for substantially reducing transient currents in the first and second switching means. In an illustrative embodiment which provides differential outputs, the charge-pump circuit further comprises a third error signal input, a fourth error signal input, a second control signal output, third means for switching the second control signal output to a current source in response to a third error signal received at the third error signal input, and fourth means for switching the second control signal output to a current sink in response to a fourth er
Boerstler David William
James Norman Karl
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
Nguyen Linh
Salys Casimer K.
Tran Toan
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