Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit
Reexamination Certificate
1999-12-08
2001-11-06
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Nonlinear amplifying circuit
Reexamination Certificate
active
06313696
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to differential buffers and more particularly to a differential buffer including first and second DC paths, each including semiconductor devices connected in cascode circuits, wherein a tap of the first path supplies bias voltage to control electrode of devices of the first and second paths and control electrodes of some devices of the second path are connected to be biased by opposite power supply voltages of the buffer.
BACKGROUND ART
FIG. 1
is a circuit diagram of a prior art differential amplifier or buffer carried by an integrated circuit chip and designed for linear analog amplification purposes. The circuit of
FIG. 1
has wide range common-mode rejection properties. The wide range common-mode rejection properties, however, are accompanied by a substantial propagation delay for the common-mode signal differentially applied to terminals
10
and
12
, which is coupled to single ended output terminal
14
.
The prior art circuit of
FIG. 1
includes driver circuit
16
and a pair of output circuits
18
and
20
. Each of circuits
16
,
18
and
20
includes at least one DC path having several three terminal semiconductor devices connected between positive DC power supply terminal
22
and ground terminal
24
. In one typical amplifier, the semiconductor devices included in each of circuits
16
,
18
and
20
are metal oxide semiconductor field effect transistors, each having a gate electrode for controlling current flow in a conducting path between source and drain electrodes. Each of output circuits
18
and
20
includes four transistors having stacked series connected source drain paths, such that circuit
18
includes field effect transistors
31
-
34
, while circuit
20
includes field transistors
35
-
38
. N-channel field effect transistors
31
and
35
are connected directly to ground terminal
24
while N-channel field effect transistors
32
and
36
are connected to ground terminal
24
through the source drain paths of transistors
31
and
35
, respectively. P-channel field effect transistors
34
and
38
are connected directly to voltage V
dd
(typically at least 3 volts) at positive DC power supply terminal
22
, and P-channel field effect transistors
33
and
37
are respectively connected to terminal
22
via the source drain paths of transistors
34
and
38
.
Driver circuit
16
includes P-channel field effect transistor
41
, having its source drain path connected to positive DC power supply voltage
22
. Transistor
41
is a current source, such that the amount of DC current flowing in its source drain path is controlled by a DC bias voltage applied to the gate of transistor
41
. The source drain path of transistor
41
drives the source drain paths of P-channel field effect transistors
42
and
43
in parallel. The source drain path of N-channel field effect transistor
44
(having its gate electrode driven by the same DC bias voltage that is applied to the gate of transistor
41
) is a current source connected to ground (i.e., negative) DC power supply terminal
24
. The source drain path of transistor
44
drives the source drain paths of N-channel field effect transistors
45
and
46
in parallel.
The gates (i.e., control electrodes) of transistors
42
and
45
are DC connected in parallel to input terminal
10
while the gates of transistors
43
and
46
are DC connected in parallel to input terminal
12
. Thereby, as the voltage at terminal
10
increases relative to ground, the voltage between the source and drain of each of transistors
42
and
45
respectively decreases and increases and vice versa for decreasing voltages at terminal
10
relative to ground; similarly, in response to increases in the voltage at terminal
12
relative to ground, the voltages across the source drain paths of transistors
43
and
46
respectively decrease and increase.
The changes in voltages across the source drain paths of transistors
42
-
46
are DC coupled to paths
18
and
20
. To this end, the drain of transistor
42
is connected to terminal
50
, between the drain of transistor
31
and the source of transistor
32
, while the drain of transistor
45
is connected to terminal
52
, between the source of transistor
33
and the drain of transistor
34
. As the voltage at terminal
10
increases relative to ground, (1) the gate source voltage of transistor
42
decreases, to decrease the voltage at the drain of transistor
42
relative to ground, whereby the voltage at terminal
50
decreases relative to ground; and (2) the gate source voltage of transistor
45
increases, to decrease the voltage at the drain of transistor
45
relative to ground, whereby the voltage at terminal
52
decreases relative to ground. The decrease in voltage at terminal
50
relative to ground increases the gate source voltage of transistor
50
to reduce the drain voltage of transistor
32
, at terminal
58
, relative to ground. The decrease in voltage at terminal
52
relative to ground decreases the gate source voltage of transistor
33
to increase the source drain voltage of transistor
33
and decrease the voltage at terminal
58
relative to ground.
Similarly, the output voltage at terminal
14
, which is between the drains of transistors
36
and
37
, goes down and up in response to the voltage at terminal
12
respectively increasing and decreasing. Common-mode rejection (i.e., cancellation at terminal
14
of like variations in amplitude and polarity of the otherwise differential or complementary variations at terminals
10
and
12
) occurs because of variations of the bias voltage at terminal
58
in response to changes in the voltage at input terminal
10
.
Since the voltages at terminals
10
and
12
vary in a complementary manner, except for common-mode variations on the voltages applied to these terminals, the voltages at terminals
50
and
52
decrease when the voltages at terminals
54
and
56
increase, and vice versa. Accordingly, in response to the complementary increasing and decreasing voltages at terminals
10
and
12
the bias voltage terminal
58
applies to the gates of transistors
35
-
38
goes down relative to ground, while the voltages at terminals
54
and
56
, at the sources of transistors
36
and
37
, go up relative to ground. As a result the gate source voltage of transistor
36
decreases to increase the voltage at the drain of transistor
36
relative to ground while the gate source voltage of transistor
37
increases to increase the voltage at the drain of transistor
37
relative to ground. Since the drains of transistors
36
and
37
are tied to output terminal
14
, the voltage at terminal
14
increases relative to ground. Simultaneously, the gate source voltages of transistors
35
and
38
respectively decrease and increase, causing the drain voltages of transistors
35
and
38
to increase relative to ground. The increased voltages at the drains of transistors
35
and
38
relative to ground are coupled through the source drain paths of transistors
36
and
37
to also cause the voltage at output terminal
14
to increase.
The voltages across transistors
35
-
38
vary in response to the voltages at terminals
10
and
12
such that the voltage at terminal
14
is an inverted replica of the voltage at terminal
12
except for the common variations at terminals
10
and
12
which are canceled in the circuit. The voltages at terminals
10
and
12
are susceptible to changing together in response to external influences being supplied to leads connected between a differential analog source (not shown) and terminals
10
and
12
. For example, if the voltages at terminals
10
and
12
both simultaneously go up by the same amount due to common mode variations, the bias voltage at terminal
58
decreases, while the voltages at terminals
54
and
56
decrease. Consequently, the voltages at the drains of transistors
35
and
38
increase relative to ground in response to the bias voltage change, while the voltages at these drains decrease in response to t
Hewlett--Packard Company
Nu Ton My-Trang
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