Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2002-09-20
2004-08-17
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S359000
Reexamination Certificate
active
06777984
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present patent specification relates to a method and apparatus for differential voltage amplifying, and more particularly to a method and apparatus for differential voltage amplifying capable of responding to a wide range of input voltage and achieving a high gain.
2. Discussion of Background
Conventionally, background differential amplifying circuits are provided with two oppositely-conductive differential transistor pairs so as to normally operate when receiving input voltages that vary within a power source voltage range. For example, Japanese Laid-Open Patent Publications, No. 04-076246 (1992), No. 08-204470 (1996), and No. 09-093055 (1997) discuss the above-mentioned background differential amplifying circuits.
FIG. 1
illustrates a background differential amplifying circuit
100
discussed in by Japanese Laid-Open Patent Publication, No. 04-076246 (1992). In
FIG. 1
, the background differential amplifying circuit
100
includes first and second power source terminals V
1
and V
2
, first and second input terminals In
1
and In
2
, first and second differential pair circuits
101
and
102
, a first current source
103
for supplying a current to the first differential pair circuit
101
, a second current source
104
for supplying a current to the second differential pair circuit
102
, first and second current mirror circuits
105
and
106
both connected to the first and second differential pair circuits
101
and
102
, and a load circuit
107
.
In
FIG. 1
, the first differential pair circuit
101
is connected to the first and second input terminals In
1
and In
2
and to the first and second output terminals OUT
1
and OUT
2
, and is biased by the first current source
103
. The second differential pair circuit
102
is connected to the first and second input terminals In
1
and In
2
and is biased by the second current source
104
. The first current mirror circuit
105
is connected to the first power source terminal V
1
, the second output terminal OUT
2
, and one output terminal of the second differential pair circuit
102
. The current mirror circuit
106
is connected to the first power source terminal V
1
, the first output terminal OUT
1
, and the other output terminal of the second differential pair circuit
102
.
FIG. 2
illustrates a detailed circuit of the background differential amplifying circuit
100
, using CMOS (complementary metal oxide semiconductor) transistors. In
FIG. 2
, the first power source terminal V
1
is fed with a negative power source voltage VSS and the second power source terminal V
2
is fed with a positive power source voltage VDD.
The background differential amplifying circuit
100
operates to achieve approximately 46 dB with the input voltages at a middle level in the range of the power source voltage in which the first and second differential pair circuits
101
and
102
can be both operable and, with other input voltages, approximately 40 dB by one of the two differential pair circuits
101
and
102
.
Generally, a differential amplifying circuit having a negative feedback circuit produces a relatively large output error, which is an error against an expected value of an output voltage when the circuit generates a relatively small gain, without considering an offset voltage inherently provided to the differential amplifying circuit. Moreover, when the differential amplifying circuit uses oppositely-conductive differential pair circuits to allow the operations in an expanded input voltage range, it produces relatively large variations in the output voltages in response to changes in the input voltages.
Therefore, the background differential amplifying circuit
100
of Japanese Laid-Open Patent Publication, No. 04-076246 (1992) may use an output circuit having a maximum gain of approximately 30 dB, thereby increasing a total gain.
In this way, it is possible to increase the gain by adding an output circuit. However, the gain generally depends on the input voltage. For example, the gain with the input voltages at a middle level in the range of the power source voltage is greatly different from that with the input voltages close to the power source voltage. With the different gains, the output errors become different typically in the case where negative feedback is applied. In particular, with the input voltages close to the power source voltage, only one of the two differential pair circuits operates and the gain of the output circuit is reduced to nearly 0 dB. Therefore, the output error may be greater.
An operational amplifier using a differential amplifying circuit commonly uses a negative feedback circuit.
FIG. 3
illustrates a background non-inverse amplifier using an operational amplifier including the background differential amplifying circuit
100
, for example. In the circuit of
FIG. 3
, when various variables are defined as an input voltage X
2
, an input voltage X
1
, an output voltage Y, resisters R
1
and R
2
, the input voltage X
2
and the output voltage Y can be expressed respectively by the following equations;
X
2
={
R
1
/(
R
1
+
R
2
)}*
Y,
and
Y=K
*(
X
1
−
X
2
+&Dgr;
V
),
wherein K represents an open loop gain and &Dgr;V represents an offset voltage, both inherent to a differential amplifying circuit. When &Dgr;V in the second equation is disregarded, the second equation is modified as follows;
Y=K
*(
X
1
−
X
2
).
Based on the first and the third equations, the output voltage Y is expressed by the following fourth equation;
Y=X
1
/{
R
1
/(
R
1
+
R
2
)+(1
/K
)}.
From the fourth equation, it is understood that the gain of the differential amplifying circuit affects the error of the output voltage relative to the input voltage and also that the output error is varied by the ratio of resisters and the amplitude of input voltage. In other words, the output error becomes relatively greater when the differential amplifying circuit has a relatively small gain or when the gain of the negative feedback circuit by resister is relatively large.
Japanese Laid-Open Patent Publication, No. 04-076246 further discusses an exemplary use of the above-described differential amplifying circuit
100
of
FIGS. 1 and 2
in the form of a voltage follower in an A/D (analog-to-digital) converter. The differential amplifying circuit
100
forms a voltage follower and is placed as a front stage to an A/D converter. In the above fourth equation, the resister R
1
is substantially infinity and the resister R
2
is substantially 0. Therefore, the output voltage Y has the error of the input voltage X
1
multiplied by K/(K+1). This indicates that the output error changes with a change of the input voltage X
1
, as in the case in which the non-inverse amplifying circuit is formed.
Japanese Laid-Open Patent Publication, No. 04-076246, indicates that the differential amplifying circuit forming a voltage follower produces variations in a range of from approximately 40 dB to approximately 70 dB. With variations of 40 dB, an output error of 1% relative to the input voltage is produced. This means that when the A/D converter and the differential amplifying circuit have the power source voltage, the A/D converter that operates for 10 bits has an error equivalent to a value ten times of the least significant bit.
For another example, there are some cases in which input voltages are amplified in order to accurately convert the input voltages with an A/D converter when the input voltages have relatively small amplitude. For example, when the non-inverse amplifying circuit of
FIG. 3
, using the background amplifying circuit
100
, is provided as a front stage to an A/D converter, the input voltages have output errors, as explained with reference to FIG.
3
. Also, the non-inverse amplifying circuit receives an adverse effect by the gain of the negative feedback circuit by the resisters in comparison with the case of the voltage follower. Accordingly, when the gain of the negative feedback circuit is relatively large, the o
Cooper & Dunham LLP
Ricoh Company LTD
Wells Kenneth B.
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