Differential amplifying circuit and multi-stage differential...

Details Differential amplifying circuit and multi-stage differential... Differential amplifying circuit and multi-stage differential...

2002-04-23

2003-04-29

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Nonlinear amplifying circuit

C327S052000

Reexamination Certificate

active

06556074

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a differential amplifying circuit and more particularly to a differential amplifying circuit that may amplify a differential voltage applied to two input terminals and to a multi-stage differential amplifying circuit using the same.
BACKGROUND OF THE INVENTION
In order to operate a system at a higher speed, large scale integration (LSI) circuits are required to operate at higher frequencies. In order to achieve higher frequencies, signals are transmitted between integrated circuits using small amplitude differential signals. However, it is important to suppress delay differences in order to operate LSI circuits at high frequencies.
In order to achieve a high frequency operation, signal transmission/reception has the following requirements:
1. A transmission signal received external to a chip should have a small amplitude, but can have a wide input voltage range (offset). By allowing the small amplitude, a delay necessitated by charging or discharging a transmission line with respect to an output load can be reduced. Thus, data transfer can be reliably transmitted at high speeds. By allowing a wide range of input, operation can be satisfactory even if noise occurs on the transmission line.
2. Data inputs are synchronized with each other. By synchronizing data inputs, processing inside of the chip can be sped up.
Adverse affects of a difference in delay on a high frequency operation will now be explained with reference to
FIGS. 9 and 10
.
FIG. 9
sets forth a circuit schematic diagram of a conventional data receiver for a LSI circuit and given the general reference character
900
.
Conventional data receiver
900
includes an input buffer block (A and B) and a flip-flop block F/F. Input buffer block A receives data inputs (D
1
P to D
8
P and D
1
N to D
8
N). Input buffer block B receives clock inputs (CLKP and CLKN). Input buffer block A provides data signals to flip-flop block F/F. The data signals provided by input buffer block A are latched in flip-flop block F/F in synchronism with a clock signal provided by input buffer block B. Input D is a data input into a flip-flop within flip-flop block F/F. Input CLK is a clock input into a flip-flop within flip-flop block F/F.
FIG. 10
is a timing diagram illustrating skews of input signals in conventional data receiver
900
.
FIG. 10
illustrates a data input signal DATA and a clock input signal CLKP. Data input signal DATA is representative of any data input signals (D
1
P to D
8
P and D
1
N to D
8
N).
As illustrated in
FIG. 10
, input buffer A has a delay difference SKEW-
1
caused by variations of data input conditions (for example, amplitude and skew of a data input signal (D
1
P to D
8
P and D
1
N to D
8
N)). Input buffer B has a delay difference SKEW-
2
caused by variations of clock input conditions (for example, amplitude and skew of a clock input signal (CLKN and CLKP)). Data input signal DATA has a setup time SETUP in which data input signal must be valid before clock input signal CLKP transitions high to ensure proper operation. Data input signal also has a hold time HOLD in which data input signal DATA must be held after clock input signal CLKP transitions high to ensure proper capture of the data value.
In view of the delay differences (SKEW-
1
and SKEW-
2
) described above, the operation frequency (CLK frequency) of flip-flop block FIF can be expressed in the following equation:
CLK
frequency=1/(SKEW-
1
+HOLD+SKEW-
2
+SETUP).
Assuming the operating frequency of flip-flop block F/F is 500 MHz and hold time HOLD and setup time SETUP are each 0.3 ns and that SKEW-
1
equals SKEW-
2
, then SKEW-
1
and SKEW-
2
=(2−0.3−0.3) ns/2=0.7 ns.
Thus, for proper operation of flip-flop block F/F, data input signals (D
1
P to D
8
P and D
1
N to D
8
N) and clock input signals (CLKP and CLKN) can only have 0.7 ns variations.
Also, in order to achieve a high frequency operation, low voltage differential signaling (LVDS) is used to transmit data from chip to chip. Thus, flip-flop block F/F must include buffers that can operate to receive signals having a small amplitude and within a wide input voltage range. LVDS uses differential data transmission by providing a forward and reverse signal transmitted at a small amplitude and within a wide input voltage range. In this way, a data interface at high speeds that is resistant to noise can be implemented.
Examples of a forward and reverse signal are illustrated in FIG.
11
.
FIG. 11
is a waveform diagram illustrating an example of a clock signal CLK and a data signal DATA. Data signal DATA includes a forward data signal DATAP and a reverse data signal DATAN. Likewise, clock signal CLK includes a forward clock signal CLKP and a reverse clock signal CLKN. Clock signal CLK and data signal DATA have an amplitude of about 100 mV and are input with a voltage offset within a range of 0 V to 2.2 V.
FIG. 12
is a circuit schematic diagram of a conventional input buffer given the general reference character
1200
. Conventional input buffer
1200
is a multi-stage differential amplifying circuit and can operate to receive input signals having a small amplitude within a wide input voltage range.
Conventional input buffer
1200
includes initial stage differential amplifying circuits (SN
1
and SP
1
), next stage differential amplifying circuit SOP, and a p-channel transistor P
1
. Conventional input buffer
1200
receives a small amplitude input signal at input terminals (H
01
and H
02
) and provides an output at output terminal N
01
.
Initial stage differential amplifying circuit SN
1
has p-channel transistors (P
2
and P
3
) and n-channel transistors (N
1
and N
2
). N-channel transistor N
1
has a source connected to ground, a drain connected to node N
13
and a gate connected to a drain of p-channel transistor P
3
and a gate of n-channel transistor N
2
. P-channel transistor P
2
has a source connected to a drain of p-channel transistor P
1
, a drain connected to node N
13
, and a gate connected to input terminal H
02
. P-channel transistor P
3
has a source connected to a drain of p-channel transistor P
1
, a drain connected to a drain of n-channel transistor N
2
and common gates of n-channel transistors (N
1
and N
2
), and a gate connected to input terminal H
01
.
Initial stage differential amplifying circuit SP
1
has p-channel transistors (P
4
and P
5
) and n-channel transistors (N
3
and N
4
). N-channel transistor N
4
has a source connected to ground, a drain connected to node N
9
and a gate connected to a drain of p-channel transistor P
4
and a gate of n-channel transistor N
3
. P-channel transistor P
5
has a source connected to a drain of p-channel transistor P
1
, a drain connected to node N
9
, and a gate connected to input terminal H
01
. P-channel transistor P
4
has a source connected to a drain of p-channel transistor P
1
, a drain connected to a drain of n-channel transistor N
3
and common gates of n-channel transistors (N
3
and N
4
), and a gate connected to input terminal H
02
.
Next stage differential amplifying circuit SOP has p-channel transistors (P
6
, P
7
and P
8
) and n-channel transistors (N
5
and N
6
). N-channel transistor N
6
has a source connected to ground, a drain connected to node NQ
50
and a gate connected to a drain of p-channel transistor P
8
and a gate of n-channel transistor N
5
. P-channel transistor P
7
has a source connected to a drain of p-channel transistor P
6
, a drain connected to node NQ
50
, and a gate connected to node N
9
. P-channel transistor P
8
has a source connected to a drain of p-channel transistor P
6
, a drain connected to a drain of n-channel transistor N
5
and common gates of n-channel transistors (N
5
and N
6
), and a gate connected to node N
13
. P-channel transistor P
6
has a source connected to a power supply VDD and a gate connected to ground.
P-channel transistor P
1
has a source connected to a power supply VDD and a gate connected to ground.
Inverter INV
1
has an input connected to node NQ
50
and

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