Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2000-05-15
2002-04-09
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000
Reexamination Certificate
active
06369652
ABSTRACT:
BACKGROUND
The present invention relates to differential amplifier circuitry, and in particular to differential amplifier circuitry for low voltage amplification.
Differential amplifiers are well-known electronic devices for amplifying a voltage difference between two input signals. The input signals are provided to a pair of transistor gates of such an amplifier, each of which regulates a larger voltage and current swing through a corresponding leg of the amplifier. The legs are independently connected to a voltage source at one end, each leg including a resistor located between the transistor and voltage source, and are together connected to a voltage or current source at an opposite end. An output signal is taken from each leg between its transistor and resistor. The transistor and resistor of each leg are designed to be matched with those of the other leg, so that any difference in voltage between the input signals generates an amplified difference in voltage between the output signals. An advantage of such a differential amplifier is that the matched pair cancels undesirable voltage swings common to input signals, which may for instance be caused by temperature variations or noise, whereas differences between the input signals are amplified.
FIG. 1
shows a prior art MOS differential amplifier
21
that may be used as a receiver for a memory unit. Similar input receivers are disclosed in U.S. Pat. No. 5,319,755 and in U.S. Pat. No. 5,977,798, which are incorporated by reference herein. First and second lines
20
and
22
having matched resistors and transistors are connected to a voltage source Vdd and current source
10
. A reference signal VREF, which has an essentially constant voltage, is input to one transistor and a data signal DATA that varies about VREF is input to the other transistor, a system sometimes termed a single-ended data receiver. Typically the input data signal swings a few volts above and below the input reference signal. When the input data signal voltage is higher than the input reference signal voltage, current flows through line
20
so that an amplified voltage OUT
0
is output on line
25
. When the input data signal voltage is lower than the reference signal voltage, current flows through line
22
so that an amplified voltage OUT_
0
is output on line
28
. The output lines
25
and
28
may be fed to a latch stage where they are clocked and stored.
To operate at higher frequencies with less power consumption, it may be desirable for the input data signal to swing by a smaller amount and to maintain lower voltage at source Vdd. With a low voltage Vdd and low input data signal swings, however, several problems may occur. Variations in rise and fall times of the output data signal make centering of the clock signal on the output data signal challenging. Setup and hold times or their tolerances might be adjusted but this has other costs and becomes more difficult at higher frequencies. Output data signals may not be equally amplified for high and low input data swings, so that a full rail voltage is not achieved for both high and low output data swings, causing errors in reading the data at both rising and falling edges.
In addition, high frequency memory devices such as those described in the above-referenced patents may employ a clocking compensation scheme including a delay locked loop (DLL), for which an input receiver setup time is matched with a clock loop phase detector setup time. For differential clock and single-ended data signals of similar amplitude, however, the differential clock may have virtually double the gain as the input receiver, so that the phase detector setup time is less than that of the input receiver.
Conventional MOS current source I
0
is shown in more detail in
FIG. 2
, and corresponding voltage and current characteristics of that current source I
0
are illustrated in FIG.
3
. The differential pair lines
20
and
22
are represented as a single variable potential V
0
. Transistor
30
has its gate held at a fixed voltage, which puts the transistor in a saturated mode for a gate-source voltage exceeding the threshold voltage of that transistor. This condition is indicated in
FIG. 3
for an output voltage and current above Vsat and Isat, respectively. For gate-source voltages below the threshold voltage the current is less, as indicated by Vlow and Ilow. With a low Vdd that may not be much greater than V
0
, the current source I
0
may operate in an unsaturated mode that amplifies a positive input data swing more than an equal magnitude negative input data swing. Other factors affecting whether current source I
0
operates in a saturated mode include the structure of transistor
30
and temperature of its operation, both of which may be impractical to change.
SUMMARY
In accordance with the present invention, a differential amplifier is provided having an unequal resistance in its legs that compensates for an unequal current flow through the legs during a logic zero data input compared to logic one data input. The unequal resistance may be provided by adding a resistor in parallel to the leg that carries greater current during amplification, lowering the resistance in that leg and also the voltage that is output from that leg. Alternatively, a variable resistance may be provided to at least one of the legs to compensate for current inequalities between the legs. The variable resistance may be provided by a transistor that is controlled by a signal indicating process, voltage and/or temperature conditions of the amplifier and adjacent circuitry. Transistors may be employed in both legs as well as in a current source for the amplifier, providing balanced current regulation for the amplifier. Such current compensated differential amplifiers may be employed for various functions, for example as input receivers or delay elements in high frequency memory systems.
REFERENCES:
patent: 4939478 (1990-07-01), Heimsch et al.
patent: 4963835 (1990-10-01), Saitoh
patent: 5142168 (1992-08-01), Matsunuga
patent: 5319755 (1994-06-01), Farmwald et al.
patent: 5821824 (1998-10-01), Mentzer
patent: 5977798 (1999-11-01), Zerbe
patent: 6002276 (1999-12-01), Wu
patent: 6072366 (2000-06-01), Maeda et al.
patent: 6118340 (2000-09-01), Koen
patent: 6125157 (2000-09-01), Donnelly et al.
Lau Benedict C.
Nguyen Huy M.
Vu Roxanne T.
Lauer Mark
Nguyen Khanh Van
Pascal Robert
Rambus Inc.
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