Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-06-06
2002-05-07
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S056000, C327S067000
Reexamination Certificate
active
06384637
ABSTRACT:
BACKGROUND
Computer components typically communicate via groups of conductors called “buses.” Such buses typically connect master devices, such as microprocessors or peripheral controllers, to slave devices, such as memory components or bus transceivers. Master and slave devices are typically connected in parallel to various locations along the bus.
Most common buses are driven by voltage-level signals. However, some modern buses are driven by current-level signals. Such “current-mode” buses offer a number of advantages, including lower signal attenuation and improved speed performance.
FIG. 1
(prior art) is a block diagram of a conventional high-speed, current-driven bus
100
. Master device
105
connects to four slave devices
115
,
120
,
125
, and
130
via a transmission line
135
. A resistor
140
terminates the end of transmission line
135
opposite master device
105
. The value of resistor
140
is matched to the impedance of transmission line
135
to minimize reflections.
Master device
105
is located at one end of transmission line
135
. Current driven by master device
105
produces a full-swing signal that propagates along transmission line
135
, past each slave device, to be dissipated by resistor
140
. In contrast, each slave device sees transmission line
135
as two lines, one extending toward the master device and the other extending toward resistor
140
. Each slave device will therefore produce a drive current that is divided between the two “branches” of transmission line
135
, generating a first half-swing signal toward master device
105
and a second half-swing signal toward resistor
140
.
Master device
105
has high input impedance, and therefore reflects half-swing signals propagated from the slave devices. Each reflected signal combines with the half-swing signal that initiated the reflection, with the resulting sum producing a full-swing signal at the input of the master device. The master device thus senses a full-swing signal despite the fact that the slaves only drive half-swing signals. Preferably, master device
105
connects to transmission line
135
in a region at or very near the point of reflection. Signal width and propagation delay dictate the extent of this region.
FIG. 2
(prior art) depicts another view of bus
100
in which slave devices
125
and
130
are omitted for brevity. Slave devices
115
and
120
are shown to include respective NMOS transistors
200
and
205
, each connected between transmission line
135
and ground potential.
In this example, slaves
115
and
120
express logic zeros by allowing transmission line
135
to transition to a relatively high voltage, pulling line
135
toward V
T
via resistor
140
, which as a value R
T
. Slaves
115
and
120
express logic-one signals on transmission line
135
by pulling the voltage level on transmission line
135
toward ground with a current I
T
. Hence, either of slaves
115
or
120
can produce a voltage swing of I
T
R
T
, so that the low output voltage V
OL
used to express a logic one on transmission line
135
is V
T
−I
T
R
T.
When master
105
successively reads logic ones (successive low voltages) from each of slaves
115
and
120
:
1. transistor
200
turns on, pulling transmission line
135
toward ground potential;
2. transistor
200
turns off, allowing resistor
140
to pull transmission line
135
toward V
T
; and
3. transistor
205
turns on, once again pulling transmission line
135
toward ground potential.
The time between transistor
200
turning off and transistor
205
turning on can be very short, particularly if slaves
115
and
120
are relatively near one another on bus
100
and bus
100
is operated at high speed.
MOS transistors
200
and
205
, under the right conditions, operate as fairly good current sources. That is to say, they provide a relatively constant current over a range of output voltages. However, when the drain-to-source voltage across transistors
200
and
205
is too low, transistors
200
and
205
no longer approximate current sources, and the resulting current fluctuations can introduce undesirable noise on line
135
. This problem is explained below in connection with
FIGS. 3 and 4
.
FIG. 3
is a graph
300
illustrating the relationship between drain current I
DS1
and drain-to-source voltage V
DS1
for transistor
200
of FIG.
2
. As can be seen in graph
300
, the drain current I
DS1
—the output current of slave device
115
—is relatively constant with variations in drain-to-source voltage V
DS1
if drain-source voltage V
DS1
is kept above a minimum level
305
. Thus, as long as the lower operation voltage V
OL
of transmission line
135
is high enough, NMOS transistors such as transistors
200
and
205
will work well as current sources.
Unfortunately, the lower the value of V
OL
, the higher the power dissipated when one of the slave devices drives a low voltage on transmission line
135
. It is therefore desirable to limit V
OL
to a level that minimizes power dissipation without affecting the ability of the slave devices to deliver clean signals with minimal reflection. In the example of
FIG. 3
, the drain-source voltage V
DS1
is maintained in a range
310
that maintains a relatively constant drain-to-source current I
DS1
while maintaining a low V
OL
of transmission line
135
.
In an exemplary bus designed by Rambus Inc. of Mountain View, California, signals on transmission line
135
range between a high V
OH
of approximately 1.8 volts and a low V
OL
of approximately 1.0 volt. Each slave, through its respective drive transistor, sinks about 28 milliamps with a channel impedance of 28 ohms to produce a bus swing of about 800 millivolts. These low voltages and currents allow this bus to operate at extraordinary speeds while dissipating relatively little power. Nevertheless, there is always a demand for improved speed performance and reduced power consumption, and thus for faster, more efficient data buses.
For additional details about the problems of transmitting data over high-speed bus systems like the one described above, see U.S. Pat. No. 5,355,391 to Horowitz et al., issued Oct. 11, 1994, which is incorporated herein by reference.
SUMMARY
The present invention is directed to a differential amplifier with reduced noise sensitivity. When the amplifier is used as a receiver on a data bus, the amplifier's reduced noise sensitivity enables the bus to operate more efficiently and at higher data rates.
A differential amplifier in accordance with the invention includes differential input and output stages. The differential input stage has a pair of adjustable resistive loads that actively alter the gain of the input stage. The differential output stage receives the output of the input stage and produces a pair of complementary output signals. These output signals are fed back to the adjustable resistive loads so that the gain of the input stage depends upon the levels of the output signals. The feedback is positive, so the voltage transfer characteristic of the inventive amplifier has different input thresholds for positive-and negative-going voltage signals. The amplifier is optimized so that the different threshold voltages mask troublesome noise sources, allowing the bus to operate at higher data rates.
This summary does not limit the invention, which is instead defined by the appended claims.
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Pp. 31
Lau Benedict C.
Nguyen Huy M.
Behiel Arthur J.
Cunningham Terry D.
Dinh Paul
Rambus
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