Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-07-23
2003-06-24
Le, Don (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000
Reexamination Certificate
active
06583665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of CMOS circuits, and specifically to the field of CMOS differential amplifiers.
2. Discussion of the Related Art
FIG. 1
shows a conventional differential amplifier with active load and a second stage output. The conventional differential amplifier illustrated in
FIG. 1
is designed for low offset voltage and noise performance. The matched p-channel device input transistors M
1
and M
2
with W/L ratios of X drive an active load, n-channel load transistors M
3
and M
4
, whose W/L ratios are X/4.
The second stage device is driven with a current source, I
2
, whose value is scaled at 10 times that of I
1
. As such, M
5
is sized at 2.5X such that the voltages across resistances Ro
1
and Ro
2
equal.
As the drain of M
5
will be the output of this two-stage amplifier, the 2.5X scaling significantly compromises its output drive and overall gain performance. Moreover, if the conventional amplifier depicted in
FIG. 1
is to be used as an operational amplifier in which the gains of input transistors M
1
and M
2
must be kept low for overall compensation purposes, then the numerical value of X may need to be selected as low as unity or perhaps even lower than unity depending on the desired Vout frequency and slew rate performance characteristics. In this case, if the input transistors are relatively small, then the output transistor will also be relatively small, thereby reducing the output drive strength of the differential amplifier.
As is apparent from the above discussion, a need exists for a differential amplifier having increased drive and gain performance.
SUMMARY OF THE INVENTION
According to the present invention, a CMOS differential amplifier includes three additional devices and an additional current source over and above conventional amplifiers. The three additional devices and current source are sized relative to one another, and relative to the sizes of the various other elements in the differential amplifier so that the size of the output device is not dependent upon the size of the input and load devices, thereby permitting increased drive and gain performance while still allowing the use of small input devices.
According to the present invention, a CMOS differential amplifier includes first and second input transistors of the second conductivity type, first and second load transistors of a first conductivity type, and a source follower transistor of the first conductivity type that is connected in series between the first input transistor and the first load transistor. For example, the first conductivity type is N-channel MOS type device, and the second conductivity type is P-channel MOS type device.
The first and second input transistors are matched in size to each other, and the first and second load transistors are matched in size to each other. The first input transistor, source follower transistor, and first load transistor form one current branch of the differential structure while the second input transistor and second load transistor form another current branch of the differential structure. A first current source supplies current to both branches of the differential structure.
An output transistor of the first conductivity type has its gate tied to the drain of the second load transistor. A second current source is coupled to the drain of the output transistor.
A first source follower bias transistor of the first conductivity type is diode connected, and its drain is coupled to the source of a second source follower bias transistor of the first conductivity type that is also diode connected. The drain of the second source follower bias transistor is coupled to the gate of the source follower transistor. A third current source is coupled to the drain of the second source follower bias transistor.
According to another aspect of the present invention, the ratio of the current from the third current source to the width-to-length ratio of the first source follower bias transistor is equal to a ratio of a current from the second current source divided by a width-to-length ratio of the output transistor. According to another aspect of the present invention, a ratio of a current from the third current source to the width-to-length ratio of the second source follower bias transistor is equal to a ratio of half of a current from the first current source to the width-to-length ratio of the source follower transistor.
These and other features, aspects, and advantages of the present invention will be apparent from the Figures read in conjunction with the Detailed Description of the Invention.
REFERENCES:
patent: 4634993 (1987-01-01), Koen
patent: 4987379 (1991-01-01), Hughes
patent: 5157349 (1992-10-01), Babanezhad
patent: 5283535 (1994-02-01), Sevenhans et al.
patent: 5515003 (1996-05-01), Kimura
patent: 6028480 (2000-02-01), Seevinck et al.
patent: 6121836 (2000-09-01), Vallencourt
I-XYS Corporation
Le Don
Mai Lam T.
Townsend and Townsend / and Crew LLP
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