Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-04-12
2002-09-24
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S543000, C323S315000
Reexamination Certificate
active
06456155
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a differential amplifier circuit suitable for use with an internal voltage generation circuit used in a semiconductor integrated circuit device to produce a predetermined internal power supply voltage.
2. Description of the Related Art
A semiconductor integrated circuit device such as a semiconductor memory device in recent years does not directly use external power supply voltage V
CC
supplied from the outside, but lowers or raises external power supply voltage V
CC
by means of an internal voltage generation circuit to produce a predetermined internal power supply voltage and supplies the produced internal power supply voltage to internal circuits to achieve reduction of power consumption and augmentation of the reliability of the device.
In order to increase the storage capacity, for example, a semiconductor memory device employs memory cells of a refined transistor size. Since this makes it impossible to apply a high voltage to transistors, a lowered voltage power supply circuit is provided in the inside of the semiconductor memory device and supplies lowered voltage V
INT
lower than the external power supply voltage to the transistors for the memory cells.
Meanwhile, raised voltage V
P
higher than external power supply voltage V
CC
is sometimes applied to a word line of a DRAM, a non-volatile memory or a like device in order to assure a desired performance. Further, a semiconductor substrate is sometimes biased to a negative voltage in order to assure a high charge retaining characteristic of a DRAM. In this manner, a semiconductor memory device internally has an internal voltage generation circuit for producing various internal power supply voltages.
FIG. 1
is a block diagram showing an example of configuration of an internal voltage generation circuit.
Referring to
FIG. 1
, the internal voltage generation circuit includes raised voltage power supply circuit
10
for producing raised voltage V
P
, lowered voltage power supply circuit
20
for producing lowered voltage V
INT
, reference voltage generation circuit
30
for supplying predetermined reference voltage V
REF
to raised voltage power supply circuit
10
and lowered voltage power supply circuit
20
, and comparison voltage generation circuit
40
for producing predetermined comparison voltage V
R
to be supplied to reference voltage generation circuit
30
in order to suppress reference voltage V
REF
from fluctuating because of a variation of the ambient temperature.
Raised voltage power supply circuit
10
includes comparator
11
, ring oscillator
12
and charge pump
13
connected in series, and divides raised voltage V
P
output from charge pump
13
by means of resistors R
1
, R
2
and feeds back divided voltage V
P2
to comparator
11
.
Comparator
11
compares divided voltage V
P2
and reference voltage V
REF
with each other. If V
P2
<V
REF
, then comparator
11
outputs a High level as an enable signal, but if V
P2
>V
REF
, then comparator
11
outputs a Low level as the enable signal.
Ring oscillator
12
includes a clock oscillator circuit and supplies a clock signal to charge pump
13
when the enable signal supplied from comparator
11
has the High level, but stops oscillation of the clock signal when the enable signal has the Low level.
Charge pump
13
produces raised voltage V
P
by multiple voltage rectification of the clock signal supplied from ring oscillator
12
. If raised voltage V
P
rises higher than a predetermined voltage, then oscillation of ring oscillator
12
stops, and consequently, raised voltage V
P
drops gradually. On the other hand, if raised voltage V
P
drops lower than the predetermined voltage, then oscillation of ring oscillator
12
is restarted, and consequently, raised voltage V
P
rises. Raised voltage V
P
is maintained constant in this manner. As seen in
FIG. 1
, raised voltage V
P
is supplied to internal circuits of the semiconductor integrated circuit device and supplied also to lowered voltage power supply circuit
20
and reference voltage generation circuit
30
.
FIG. 2
is a circuit diagram showing an example of configuration of the lowered voltage power supply circuit shown in FIG.
1
.
Referring to
FIG. 2
, lowered voltage power supply circuit
20
includes output transistor
21
formed from an N-channel MOSFET supplied with external power supply voltage V
CC
for supplying lowered voltage V
INT
to an internal circuit serving as a load, differential amplifier circuit
22
supplied with raised voltage V
P
for outputting a control voltage for controlling the gate voltage of output transistor
21
, and phase compensation capacitor C
P
interposed between an output contact of output transistor
21
and the ground potential for preventing oscillation of lowered voltage power supply circuit
20
.
Differential amplifier circuit
22
includes transistors Q
11
, Q
12
formed from P-channel MOSFETs connected commonly at the gates thereof, transistors Q
13
, Q
14
formed from N-channel MOSFETs connected in series to transistors Q
11
, Q
12
and connected at the respective sources thereof, and constant current source
23
for supplying predetermined current to transistors Q
11
to Q
14
. Transistors Q
11
, Q
12
form a current mirror circuit by connection of the gate and the drain of transistor Q
11
so that values of Current flowing between the source-drain of transistors Q
11
, Q
12
may be equal to each other.
Reference voltage V
REF
supplied from reference voltage generation circuit
30
is input to the gate of transistor Q
13
connected to non-inverted input terminal
24
, and the drain voltage of transistor Q
14
which is an output of differential amplifier circuit
22
is applied to the gate of output transistor
21
. Output voltage V
INT
(lowered voltage) output from the drain of output transistor
21
is fed back to the gate of transistor Q
14
connected to inverted input terminal
25
of differential amplifier circuit
22
.
Differential amplifier circuit
22
amplifies a difference between input voltages applied to inverted input terminal
25
and non-inverted input terminal
24
and outputs the amplified input voltage difference from the drain of transistor Q
14
. Accordingly, lowered voltage power supply circuit
20
shown in
FIG. 2
operates so that, when output voltage V
INT
is lower than reference voltage V
REF
, the potential at node A of differential amplifier circuit
22
rises and source-gate voltage V
GS
of output transistor
21
increases, and consequently, output voltage V
INT
rises. On the other hand, when output voltage V
INT
is higher than reference voltage V
REF
, the potential at node A of differential amplifier circuit
22
drops and source-gate voltage V
GS
of output transistor
21
decreases, and consequently, output voltage V
INT
is lowered by the load. In other words, differential amplifier circuit
22
is controlled so that output voltage V
INT
may become equal to reference voltage V
REF
.
FIG. 3
is a circuit diagram showing an example of configuration of the reference voltage generation circuit shown in FIG.
1
.
Referring to
FIG. 3
, reference voltage generation circuit
30
includes output transistor
31
supplied with external power supply voltage V
CC
for supplying reference voltage V
REF
to raised voltage power supply circuit
10
and lowered voltage power supply circuit
20
which serves as a load, differential amplifier circuit
32
supplied with raised voltage V
P
for outputting a control voltage for controlling the gate voltage of output transistor
31
, and phase compensation capacitor C
P
interposed between an output contact of differential amplifier circuit
32
and the ground potential for preventing oscillation. Differential amplifier circuit
32
has a configuration similar to that of differential amplifier circuit
22
for the lowered voltage power supply circuit shown in FIG.
2
.
Comparison voltage V
R
supplied from comparison voltage generation circuit
40
is input to non-inverted input terminal
33
Callahan Timothy P.
Englund Terry L.
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