Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-05-31
2003-04-01
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S253000, C330S259000
Reexamination Certificate
active
06542033
ABSTRACT:
TECHNICAL FIELD
The present invention relates to push-pull amplifier circuits that comprise CMOS transistors and perform class-AB operations. The device of the present invention relates to differential amplifier circuits that are suitable for use in power conservation type devices such as portable telephones, which should secure the prescribed service life for batteries.
BACKGROUND ART
Conventionally, push-pull amplifier circuits comprising CMOS transistors have been widely used.
FIG. 4
is a circuit diagram of a conventional device. In this figure, an input circuit
1
provides transistors T
2
and T
5
for constituting a current mirror circuit, a transistor T
6
whose gate terminal inputs a positive input signal +IN, and a transistor T
3
whose gate terminal inputs a negative input signal −IN. The current mirror circuit is connected with a positive voltage source V
DD
. A bias circuit
2
comprises a resistor R
1
for setting an operation bias point, and a transistor Ti for generating bias voltage, wherein it is inserted between the positive voltage source V
DD
and reference voltage V
SS
. A transistor T
4
is an element that supplies a bias current to the input circuit
1
. A level shift circuit
3
comprises transistors T
9
and T
10
. An output circuit
4
comprises output transistors T
7
and T
8
as well as an output terminal OUT.
In the device having the aforementioned configuration, the voltage that is calculated by subtracting voltage drop of the transistor T
1
from the difference voltage between the positive voltage source V
DD
and reference voltage V
SS
is applied to the resistor R
1
in the bias circuit
2
, so that an electric current is forced to flow into a series circuit in which the resistor R
1
and the transistor T
1
are connected to an NB node. The magnitude of this current is supplied as the form of bias voltage to each element via the NB node, thus determining an operation point for each element. In the input circuit
1
, the transistors T
3
and T
6
are identical to each other in characteristics, and the transistors T
2
and T
5
are identical to each other in characteristics. An N
3
node is a common connection point between the transistors T
5
and T
6
, so that an N
3
node voltage V
N3
may greatly vary in response to variations of the difference voltage (V
+IN
−V
−IN
) between the positive input signal voltage V
+IN
and negative input signal voltage V
−IN
. That is, the voltage gain is increased by using the negative resistance, which is established by drain currents I
D
and drain-source voltages V
DS
of the transistors T
5
and T
6
, as an active load.
The output circuit
4
is an active load in which the output transistor T
8
acts as a load for the output transistor T
7
, wherein a signal is applied through the transistor T
9
to the output transistor T
8
to operate. The current of the output transistor T
7
varies in response to the N
3
node voltage V
N3
. A capacitor Cc is reduced in gain due to high frequencies to avoid oscillation. Variations of this current is converted to a signal having a large amplitude by the active load, so that the signal is output from the output terminal OUT. The level shift circuit
3
converts the difference voltage (V
+IN
−V
−IN
), supplied from the input circuit
1
, in voltage level and supplies it to the output circuit
4
.
In order to perform a class-A operation ensuring linear signal amplification, bias currents are normally forced to flow, regardless of the existence of the input signal. On the other hand, in the case of the high power amplifier circuit that performs a class-B operation, the bias voltage is set to zero so as to avoid the bias current flowing in a non-signal mode. However, the class-B operation may cause the crossover distortion due to the non-linearity of the characteristic in proximity to zero current. Therefore, in order to avoid occurrence of the crossover distortion, a class-AB operation is used to allow a small bias current to flow.
However, the conventional technology has a problem in that characteristic variations may easily occur because the operation point of the output circuit would vary due to manufacture differences and power variations. Therefore, a small bias current is forced to flow in a non-signal mode in order to secure some margins. It is required that portable telephones should secure one-hundred hours or more per a single battery with respect to the reception wait time; hence, the bias current should be extremely reduced in a non-signal mode. The present invention is provided to solve the aforementioned problems. It is an object of the invention to provide a differential amplifier circuit in which the operation point of the output circuit is stable, and which requires an extremely small amount of bias current compared to the maximal output current in a non-signal mode.
DISCLOSURE OF INVENTION
A differential amplifier circuit of the present invention solving the aforementioned problems comprises as shown in
FIG. 1
an input circuit
10
for producing a difference voltage signal between the positive input signal and negative input signal, a feedback bias circuit
20
that inputs the difference voltage signal supplied from the input circuit
10
to provide a bias voltage corresponding to the difference voltage signal and that performs feedback controls on the bias voltage by feeding back an output current, an output circuit
30
for supplying the load with the output current corresponding to the bias voltage, and a current detection circuit
40
that detects the output current to provide it to the feedback bias circuit
20
, wherein class-AB amplification is performed in such a way that the bias voltage has a current value close to zero when the difference voltage signal is substantially zero.
In the device having the aforementioned configuration, class-AB amplification is performed in such a way that when no signal is applied to the input circuit
10
, the feedback bias circuit
20
supplies the output circuit with the bias voltage whose current consumed is small compared to the maximal output current. The current detection circuit
40
detects the output current to feed back it to the feedback bias circuit
20
, which in turn performs feedback controls on the bias voltage by feeding back the output current. Therefore, even though manufacture differences and power variations exist, it is possible to obtain a differential amplifier circuit in which the operation point of the output circuit is stable.
Preferably, the input circuit
10
comprises a first transistor MP
2
whose gate terminal inputs a positive input signal, and a second transistor MP
1
whose gate terminal inputs a negative input signal, wherein source terminals of the first and second transistors are connected to a positive voltage source V
DD
via a constant current source transistor MP
3
, and their drain terminals are connected to the aforementioned feedback bias circuit. Both the first and second transistors are identical to each other in characteristics; thus, it is possible to produce an accurate difference voltage signal.
Preferably, the output circuit
30
comprises a first output transistor MP
17
and a second output transistor MN
11
that are connected between the positive voltage source V
DD
and reference voltage GND, V
ss
, wherein the bias voltage supplied from the feedback bias circuit
20
is applied to source terminals of the first and second output transistors, and the first and second output transistors are commonly connected to an output terminal. Due to an active load effect of the first and second output transistors, small variations of the bias voltage are converted into a signal having a large amplitude, which is output from the output terminal.
Preferably, the current detection circuit
40
comprises a first current detection transistor MP
16
in which the bias voltage applied to the first output transistor MP
17
is supplied to the gate terminal, and the voltage of the positive voltage source V
DD
is supplied to t
Nguyen Patricia
Pascal Robert
Pillsbury & Winthrop LLP
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