Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
1999-09-17
2001-08-14
Mottola, Steven J. (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000
Reexamination Certificate
active
06275107
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a differential amplifier circuit or differential input circuit formed in a semiconductor substrate, and more particularly, to a differential amplifier circuit or differential input circuit which suppresses the effects of variations in transistor characteristics caused by variations in manufacture processing and is not influenced by level fluctuations in the differential input signal.
Moreover, the present invention relates to a pull up-type differential bus driver and a differential bus driving method suitable for use in cases where differential signals are transmitted between semiconductor chips.
2. Description of the Related Art
Differential amplifier circuits or differential input circuits (hereinafter, simply called differential amplifier circuits) comprising a pair of MOS transistors, differential inputs being supplied respectively to the gates thereof and an output being generated at the drains thereof, are widely used. In a differential amplifier circuit of this kind, a current source is connected to the source electrodes of a pair of MOS transistors and supplies a fixed current thereto, differential inputs supplied to the gates are compared and the conductivity of one of the pair of MOS transistors is raised whilst the conductivity of the other transistor is lowered.
In cases where signals of small amplitude, such as 100 mv, for example, or differential input signals having a large fluctuation in the central voltage of the amplitude are supplied as differential inputs, generally, the operation of the differential amplifier circuit is stabilized by holding the current from the aforementioned current source at a uniform value as far as possible.
FIG. 1
is a diagram showing an example of a conventional differential amplifier circuit. This differential amplifier circuit comprises: a pair of N-channel input MOS transistors N
1
, N
2
, wherein differential inputs IN, /IN are supplied respectively to the gates thereof and the sources thereof are connected mutually; load circuits L
1
, L
2
provided between the drains thereof and a first power source Vdd; and a current source I
1
provided between the sources and the second power source Vss. An amplified output is generated at the drain terminal nl of transistor N
2
in accordance with the differential inputs IN, /IN. This output nl is supplied to the input of a CMOS inverter consisting of a P-channel MOS transistor P
3
and N-channel MOS transistor N
3
.
FIG. 2
is a diagram showing a further example of a conventional differential amplifier circuit. This differential amplifier circuit also comprises a pair of input MOS transistors N
1
, N
2
, load circuits L
1
, L
2
, and a current source I
1
. Moreover, in the differential amplifier circuit in
FIG. 2
, the drain terminal n
1
of the transistor N
2
is connected to the gate of a P-channel output MOS transistor P
4
, and the junction point n
3
between the output MOS transistor P
4
and a current source I
2
is supplied to the input of a CMOS inverter. This circuit differs from the differential amplifier circuit in
FIG. 1
in that the signal n
3
, which is an inverse amplification of the signal from drain terminal n
1
, is supplied to a CMOS inverter.
In the aforementioned conventional differential amplifier circuit, if the voltage of input IN is lower than the inverse input /IN, then transistor N
2
switches on and the voltage of node n
1
assumes level L, whereas if, conversely, the voltage of input IN is higher than the inverse input /IN, then transistor N
2
switches off and the voltage of node n
1
assumes level H. In the differential amplifier circuit in
FIG. 1
, level L or level H is generated at output n
2
of the inverter, in accordance with level H or level L at node n
1
. In the differential amplifier circuit in
FIG. 2
, level L or level H is generated at node n
3
and level H or level L is generated at the output n
2
of the inverter, respectively, in accordance with level H or level L at node n
1
.
FIG. 3
is a diagram illustrating problems associated with the prior art examples described above.
FIG. 3A
shows the relationship between the outputs n
1
, n
3
of the aforementioned differential amplifier circuit and the threshold value VthC of the CMOS inverter, and
FIG. 3B
shows the voltage level of the output n
2
of the CMOS inverter corresponding to same.
The outputs n
1
, n
3
of the differential amplifier circuit assume level H and level L having prescribed amplitudes, without performing a full swing between the power sources Vdd and Vss. In contrast to this, the output n
2
of the CMOS inverter does make a full swing, assuming either level H, which is the level of the higher power source Vdd, or level L, which is the level of the lower power source (ground) Vss. On the other hand, if the differential amplifier circuit is formed as part of an integrated circuit on a semiconductor substrate, then variations will arise in the characteristics of the MOS transistors due to variations in processing. For example, if a variation in characteristics arises whereby the drive capacity of N-channel MOS transistors is raised, then the impedance of the MOS transistor N
2
when conducting will fall, and hence the central voltage of the amplitude at node n
1
will tend to fall. In other words, it will deviate from the solid line in FIG.
3
and follow the dotted line. If, conversely, a variation in characteristics arises whereby the drive capacitor of the N-channel MOS transistor is reduced, then the impedance of the MOS transistor N
2
when conducting will rise, and hence the central voltage of the amplitude at node n
1
will tend to rise. In other words, it will deviate from the solid line in FIG.
3
and follow the broken line.
Upward or downward fluctuation in the central value of the amplitude of output n
1
caused by variations in processing is particularly notable in cases where P-channel MOS transistors are used in the load circuits L
1
, L
2
and the drive capacity of the P-channel MOS transistors varies in the opposite direction to the variation in the drive capacity of the N-channel MOS transistors. Even in cases where P-channel output MOS transistors are provided as illustrated in
FIG. 2
, the central value of the amplitude at output n
3
will similarly vary either in an upward or downward direction due to variations in processing.
If the outputs n
1
or n
3
from the differential amplifier circuit vary as illustrated in
FIG. 3
, then either one of the P-channel transistor P
3
or N-channel transistor N
3
in the subsequent CMOS inverter driven by these outputs n
1
, n
3
, will not be able completely to assume a non-conducting state, thereby resulting in a through current from power source Vdd to Vss in the CMOS inverter. The generation of through current in this way, in addition to increasing power consumption, also leads to problems in that the output n
2
of the CMOS inverter cannot be amplified completely to the power source level.
Moreover, to describe a second problem, when the outputs n
1
, n
3
of the differential amplifier circuit are higher than the threshold voltage VthC of the CMOS inverter, as illustrated in
FIG. 3
, the output thereof assumes level L, whereas when outputs n
1
, n
3
are lower than VthC, then the output assumes level H. However, if the voltage of the outputs n
1
, n
3
of the differential amplifier circuit vary upwards or downwards as shown in
FIG. 3
due to processing in manufacture, then the timing of level H or level L of the input with respect to the threshold voltage of the CMOS inverter will differ. As a result, the input rise propagation delay time and the input fall propagation delay time in the CMOS inverter will run contrary to each other, leading to significant variations in characteristics during high-speed operation. Since the threshold voltage VthC of the CMOS inverter is a value determined by the ratio of current values in the P-channel transistor P
3
and the N-channel transistor N
3
, this threshold voltage VthC also var
Maeda Junko
Naka Naoaki
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitisu Limited
Mottola Steven J.
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