Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-03-27
2003-04-22
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S254000, C330S257000, C330S261000
Reexamination Certificate
active
06552611
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-086381, filed Mar. 27, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a differential amplifier which is fundamental in processing an analog signal in a MOS integrated circuit and to a filter circuit using the differential amplifier as a transconductance circuit.
To process an analog signal with high quality, it is necessary to cause the circuit to operate linearly. In general, however, it is difficult to realize an analog circuit with good linearity using a CMOS circuit. The reason for this is that the approach of expanding the linear range using resistances is not effective, because the MOS transistor has a lower gm (transconductance) than that of the bipolar transistor, and that the MOS transistor itself has a square-law characteristic in the normal operating region. Thus, the approach of realizing an amplifier with a wide linearity by taking advantage of the square-law characteristic of the MOS transistor has been proposed.
A basic one of this approach has been proposed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 10-65461. The principle of the approach is shown in FIG.
1
. The circuit of
FIG. 1
is composed of a pair of MOS transistors M
1
, M
2
whose sources are grounded. Consider a case where a complete differential signal is inputted to the circuit. It is assumed that both of the transistors M
1
and M
2
are operating in the saturation region (pinch-off region). To simplify the explanation, the short channel effect is not taken into consideration. At this time, using the values of the main parameters, k and Vth, the characteristic of each of the MOS transistors M
1
, M
2
can be expressed as:
I=(
k/
2)(V
GS
−Vth
)
2
(1)
where I is the drain current, V
GS
is the gate-source voltage, Vth is the threshold voltage inherent to the transistor, and k is the constant &mgr;C
OX
W/L where W is the gate width, L is the gate length, C
OX
is the gate capacity, and &mgr; is the carrier mobility of the channel.
Using equation (1), the descriptive equations for the operation of the transistors M
1
and M
2
can be expressed as follows:
M
1
: Iout+=(
k/
2)(V
GS1
−Vth
)
2
(2)
M
2
: Iout−=(
k/
2)(V
GS2
−Vth
)
2
(3)
Subtracting equation (3) from equation (2) gives:
Iout
+
-
Iout
-=
(
k
/
2
)
(
V
GS1
+
V
GS2
-
2
Vth
)
(
V
GS1
-
V
GS2
)
=
k
(
VB
-
Vth
)
Vin
(
4
)
where V
GS1
, V
GS2
are the gate-source voltages of the MOS transistors M
1
and M
2
, respectively, Vin is the input signal (differential input voltage), and V
B
is the midpoint voltage of the input signal. Because the input signal is assumed to be a complete differential signal, the relationship of V
GS1
+V
GS2
=2V
B
=constant is used.
Since k(V
B
−Vth) is constant in equation (4), it is understood that the differential current of the output is completely proportional to the input voltage. That is, taking out the output in the form of the differential current enables the completely linear characteristic to be realized as the input/output characteristic, while assuring a wider linearity. Actually, as long as the input conditions are fulfilled, the linear range can be expanded to the extent that the transistors M
1
and M
2
are kept in the saturation region.
Another necessary condition for processing an analog signal with high accuracy is that the differential circuit has a high common mode rejection capability. In the circuit of
FIG. 1
, which provides differential operation, the common mode gain is obviously equal to the voltage gain of the single common-source MOS transistor and very high. In other words, the circuit has a low common mode rejection capability. Thus, when the input signal includes no in-phase components, there is no problem. When the input signal includes in-phase components, however, the components are amplified and appear at the output. Therefore, when the circuit shown in
FIG. 1
is used as it is, its application is limited because its common mode rejection capability is low.
To overcome this disadvantage, a circuit system with a high common mode rejection capability has been proposed in Jpn. Pat. Appln. KOKAI Publication No. 8-32372 (or Japanese Pat. No. 2638492). The circuit described in the publication is shown in
FIG. 2. A
general approach of providing a circuit with a high common mode rejection capability is to construct the input stage using a differential circuit. In the conventional circuit of
FIG. 2
, the input stage is composed of two pairs of differential circuits: one pair includes MOS transistors M
11
and M
12
and the other pair includes MOS transistors M
13
and M
14
. The coupled point of the sources of the transistors M
11
and M
12
is biased by a current source
10
. The coupled point of the sources of the transistors M
13
and M
14
is biased by a current source
11
.
With this configuration, an input signal voltage of V
1
is normally distributed to the MOS transistors M
11
and M
12
and the MOS transistors M
13
and M
14
in the form of a variation in the gate-source voltage. Since the ratio of the distribution varies dynamically according to the input signal voltage V
1
, the linear output for the input cannot be drawn from the drain current of each pair. As a result, a linearizing approach as shown in the circuit of
FIG. 1
cannot be applied.
In
FIG. 2
, to overcome this problem, the drain current of the MOS transistor M
12
is returned by a current mirror circuit composed of MOS transistors M
15
and M
16
and another current mirror circuit composed of MOS transistors M
18
and M
17
, and is added to the current source
10
. In addition, the drain current of the MOS transistor M
13
is returned by a current mirror circuit composed of MOS transistors M
20
and M
21
and another current mirror circuit composed of MOS transistors M
23
and M
22
, and is added to the current source
11
.
With this configuration, the drain current of the MOS transistor M
12
including a variation in the signal is all supplied from the MOS transistor M
17
, with the result that the current flowing through the MOS transistor M
11
becomes a constant current
10
. Similarly, the drain current of the MOS transistor M
13
including a variation in the signal is all supplied from the MOS transistor M
22
, with the result that the current flowing through the MOS transistor M
14
becomes a constant current I
0
. Consequently, the gate-source voltage of the MOS transistor M
11
depends only on the constant current I
0
and becomes a constant voltage independent of the input signal voltage V
1
. The gate-source voltage of the MOS transistor M
14
depends only on the constant current I
0
and becomes a constant voltage independent of the input signal voltage V
1
.
Therefore, all the input signal voltage V
1
is applied between the gate and source of the MOS transistor M
12
and between the gate and source of the MOS transistor M
13
. The voltage applied between the gate and source of each of the MOS transistors M
11
to M
14
is expressed by the following equations:
M
11
: I
0
=(
k/
2)(V
GS11
−Vth
)
2
(5)
M
12
: Id
12
=(
k/
2)(V
GS11
−V
1
−Vth
)
2
(6)
M
13
: Id
13
=(
k/
2)(V
GS14
+V
1
−Vth
)
2
(7)
M
14
: I
0
=(
k/
2)(V
GS14
−Vth)
2
(8)
where Id
12
and Id
13
are the drain currents of the MOS transistors M
12
and M
13
.
From equation (5) and equation (8), V
GS14
=V
GS11
holds. Taking this into account, subtracting equation (6) from equation (7) gives:
Id
13
−Id
12
=2
k
(V
GS11
−Vth
)V
1
(9)
Since V
GS11
=constant, equation (9) means that the differential current of the output is completely prop
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Shingleton Michael B
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