Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
1998-11-12
2001-11-13
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S257000
Reexamination Certificate
active
06316998
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a differential amplifier and a method of compensation, and more particularly it relates to a differential amplifier that is suitable for use in the pre-amplifier of an audio amplifier.
2. Description of the Related Art
A known fully differential amplifier is as shown in
FIG. 2
(for example as in Okamoto, T. et al, “A 16b Oversampling CODEC with filtering DSP”, ISSCC Dig. Tech. Papers, pp 74-77, Feb. 1991).
The fully differential amplifier of the past as shown in
FIG. 2
is formed by a first MOSFET of a first polarity (MP
1
), the gate of which is connected to a non-inverting input terminal (
103
), a second MOSFET of the first polarity (MP
2
), the gate of which is connected to an inverting input terminal (
104
) and the source of which is connected to the source of MP
1
, a third MOSFET of the first polarity (MP
3
), the source of which is connected to a first power supply (
101
) and the drain of which is connected to the source of MP
1
, a fifth MOSFET of the first polarity (MP
5
), the source of which is connected to the first power supply (
101
) and the gate of which is connected to the drain of MP
5
, a sixth MOSFET of the first polarity (MP
6
), the source of which is connected to the first power supply (
101
), the gate of which is connected to the gate of MP
5
, and the drain of which is connected to a non-inverting output terminal (
105
), a seventh MOSFET of the first polarity (MP
7
), the gate of which is connected to the non-inverting input terminal (
103
), an eighth MOSFET of the first polarity (MP
8
), the gate of which is connected to the inverting input terminal (
104
) and the source of which is connected to the source of MP
7
, a ninth MOSFET of the first polarity (MP
9
), the drain of which is connected to the source of MP
7
and the gate of which is connected to the common-mode feedback input terminal (
107
), an eleventh MOSFET of the first polarity (MP
11
), the source of which is connected to the first power supply (
101
) and the gate of which is connected to the drain of MP
11
, a twelfth MOSFET of the first polarity (MP
12
), the source of which is connected to the first power supply (
101
), the gate of which is connected to the gate of MP
11
, and the drain of which is connected to the non-inverting output terminal (
106
), a thirteenth MOSFET of the first polarity (MP
13
), the source of which is connected to the first power supply (
101
) and the gate and the drain of which is connected to the gate of MP
3
, a first MOSFET of a second polarity (MN
1
), the source of which is connected to a second power supply (
102
), and the gate and drain of which are connected to the drain of MP
7
, a second MOSFET of the second polarity (MN
2
), the source of which is connected to the second power supply, the gate of which is connected to the drain of MN
1
, and the drain of which is connected to the drain of MP
2
, a third MOSFET of the second polarity (MN
3
), the source of which is connected to the second power supply (
102
), the gate of which is connected to the gate and drain of MN
1
, and the drain of which is connected to the drain of MP
5
, a sixth MOSFET of the second polarity (MN
6
), the source of which is connected to the second power supply (
102
), the gate of which is connected to the drain of MN
2
, and the drain of which is connected to the drain of MP
6
, a seventh MOSFET of the second polarity (MN
7
), the source of which is connected to the second power supply (
102
), and the gate and the drain of which are connected to the drain of MP
8
, an eighth MOSFET of the second polarity (MN
8
), the source of which is connected to the second power supply (
102
), the gate of which is connected to the gate and the drain of MN
7
, and the drain of which is connected to the drain of MP
1
, a ninth MOSFET of the second polarity (MN
9
), the source of which is connected to the second power supply (
102
), the gate of which is connected to the gate and the drain of MN
7
, and the drain of which is connected to the drain of MP
11
, a twelfth MOSFET of the second polarity (MN
12
), the source of which is connected to the second power supply (
102
), the gate of which is connected to the drain of MN
8
, and the drain of which is connected to the drain of MP
12
, a thirteenth MOSFET of the second polarity (MN
13
), the source of which is connected to the second power supply (
102
), the gate and the drain of which are connected to one end of a constant-current power supply (
108
), and a fourteenth MOSFET of the second polarity (MN
14
), the source of which is connected to the second power supply (
102
), the gate of which is connected to the gate and the drain of MN
13
, and the drain of which is connected to the drain of MP
13
. In addition to the above-described MOSFETs, this circuit has a constant-current power supply (
108
), one end of which is connected to the first power supply (
101
), and the other end of which is connected to the drain of MN
13
, a first resistor (R
1
), one end of which is connected to the gate of MN
6
, a first capacitor (C
1
), one end of which is connected to the inverting output terminal (
105
) and the other end of which is connected to the other end of the first resistor (R
1
), a second resistor (R
2
), one end of which is connected to the gate of MN
12
, a second capacitor (C
2
), one end of which is connected to the non-inverting output terminal (
106
) and the other end of which is connected to the other end of the second resistor (R
2
), a third resistor (R
3
), one end of which is connected to the gate of MN
3
, a third capacitor (C
3
), one end of which is connected to the drain of MP
5
, and the other end of which is connected to the other end of the third resistor (R
3
), a fourth resistor (R
4
), one end of which is connected to the gate of MN
7
, and a fourth capacitor (C
4
) one end of which is connected to the drain of MN
9
, and the other end of which is connected to the other end of the fourth resistor (R
4
).
The operation of the above-noted fully differential amplifier will be described with reference to FIG.
2
. Because this amplifier is a fully differential amplifier, the description will be divided between the inverting output circuit section and the non-inverting output circuit section. First, referring to the inverting output circuit section, the constant-current transistor MP
3
, the differential input pair MP
1
, MP
2
, MP
7
and MP
2
and the load transistors MN
1
and MN
2
form a differential input gain stage, the non-inverting output signal of which is transmitted to the gate of MN
6
and the inverting output signal of which is transmitted to the gate of MP
6
via the inverting signal transmitting circuit formed by MOSFETs MN
3
and MP
5
, thereby forming a two-stage push-pull output amplifier.
The desired phase margin is achieved by addition of the first compensation circuit that is formed by R
1
and C
1
between the drain of MP
2
and the non-inverting output terminal (
105
), and by addition of the second compensation circuit formed by R
3
and C
3
between the inverting output of the differential input stage and the output of the inverting signal transmitting circuit. In the same manner with regard to the non-inverting output as well, the constant-current transistor MP
3
, the differential input pair MP
1
, MP
2
, MP
8
and MP
1
and the load transistors MN
7
and MN
8
form a differential input gain stage, the non-inverting output signal of which is transmitted to the gate of the MN
12
, and the inverting output signal of which is transmitted to the gate of MP
12
via the inverting signal transmitting circuit formed by MOSFETs MN
9
and MP
11
, thereby forming a two-stage push-pull output amplifier. The desired phase margin is achieved by addition of a compensation circuit that is formed by R
2
and C
2
between the non-inverting output of the differential input stage and the output of the drive stage, and by addition of a compensation circuit formed by R
4
and C
4
between the inverting output
Foley & Lardner
NEC Corporation
Nguyen Khanh Van
Pascal Robert
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