Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1997-03-20
1998-08-04
Fahmy, Wael
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257506, 257499, 257640, 257649, H07L 2176
Patent
active
057897930
ABSTRACT:
A method for fabricating a semiconductor device comprising fabricating a sacrificial wafer having a substrate wafer which includes a diffused layer and one or two epi layers. The sacrificial wafer is fusion bonded to a separately fabricated carrier/handle wafer having a layer of oxide on its surface, to form a composite wafer. Selective regions of the composite wafer are anodized and oxidized to form a plurality of wells separated from each other by a dielectric insulating layer. Next, N- epi regions above P+ epi regions are removed or alternatively, P+ diffused layers are removed from above an N- epi layer in selected regions. Finally, P- or N- single crystal silicon is grown back to the removed regions, depending on how the regions were removed. If N- single crystal is grown back to the removed regions, a high temperature drive-in is employed to finish the processing. The final structure contains N and P regions which are dielectrically isolated from each other and from the substrate. The isolated well structure can now be used to house circuit elements such as resistors, diodes, transistors, scrs, etc., individually or multiply as desired.
REFERENCES:
patent: 3954522 (1976-05-01), Roberson
patent: 5362667 (1994-11-01), Linn et al.
patent: 5442223 (1995-08-01), Fujii
Translation of JP 2-271567 to Shirato.
Drum, C.M. et al., "A Lav-Stress Insulating Film on Silicon By Chemical Vapor Deposition", Journal of Applied Physics, vol. 39, No. 9, Aug. 1968, pp. 4458-4459.
Bemis Andrew V.
Kurtz Anthony D.
Fahmy Wael
Hardy David B.
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