Dielectric recess for wafer-to-wafer and die-to-die metal...

Details Dielectric recess for wafer-to-wafer and die-to-die metal... Dielectric recess for wafer-to-wafer and die-to-die metal...

2005-05-03

2005-05-03

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S459000, C438S692000

Reexamination Certificate

active

06887769

ABSTRACT:
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.

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