Dielectric ledge for high frequency devices

Details Dielectric ledge for high frequency devices Dielectric ledge for high frequency devices

2008-06-26

2010-10-19

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S700000, C438S733000, C257SE21170, C257SE21042, C257SE21085, C257SE21092, C257SE21126, C257SE21127, C257SE21182, C257SE21227, C257SE21247, C257SE21248, C257SE21320, C257SE21585

Reexamination Certificate

active

07816221

ABSTRACT:
High frequency performance of (e.g., silicon) bipolar devices (40, 100, 100″) is improved by reducing the capacitive coupling (Cbc) between the extrinsic base contact (46) and the collector (44, 44′, 44″). A dielectric ledge (453, 453′) is created during fabrication to separate the extrinsic base contract (46) from the collector (44, 44′, 44″) periphery (441). The dielectric ledge (453, 453′) underlies the transition region (461) where the extrinsic base contact (46) is coupled to the intrinsic base. (472) During device fabrication, a multi layer dielectric stack (45) is formed adjacent the intrinsic base (472) that allows the simultaneous creation of an undercut region (457, 457′) in which the intrinsic base (472) to extrinsic base contact (46) transition region (461) can be formed. The transition region (461) formed in the cavity (457, 457′) overlies the dielectric ledge (453, 453′) which separates it from the collector (44, 44′, 44″) periphery (441), thereby reducing the base-collector junction capacitance (Cbc). fMAXof the device is significantly increased.

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PCT Application No. PCT/US2009/038550; Search Report and Written Opinion mailed Sep. 29, 2009.

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