Dielectric isolation using shallow oxide and polycrystalline sil

Details Dielectric isolation using shallow oxide and polycrystalline sil Dielectric isolation using shallow oxide and polycrystalline sil

1977-02-28

1980-01-15

Wojciechowicz, Edward J.

357 49, 357 51, 357 52, 357 55, 357 59, H01L 2704

Patent

active

041841727

ABSTRACT:
A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means.
This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n-epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide "bump" at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

REFERENCES:
patent: 4009484 (1977-02-01), Ogiue et al.
patent: 4016596 (1977-04-01), Magdo et al.

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