Dielectric isolation type semiconductor device and method...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...

Reexamination Certificate

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C257S347000

Reexamination Certificate

active

07135752

ABSTRACT:
A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A semiconductor substrate (1) and an n−type semiconductor layer (2) are bonded to each other through a buried oxide film layer (3). A first porous oxide film area (10) is formed in the semiconductor substrate in a state contacting with the buried oxide film layer. A power device is formed on the n−type semiconductor layer. The first porous oxide film area is formed in an area including a location right under a first main electrode (6) and extending from the first main electrode side up to a range of more than 40% of a distance (L) between the first and second main electrodes (6, 7).

REFERENCES:
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patent: 2004/0119132 (2004-06-01), Akiyama et al.
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patent: 9-45762 (1997-02-01), None
patent: 3435930 (2003-08-01), None
Kazuo Imai, “A New Dielectric Isolation Method Using Porous Silicon”, Solid-State Electronics , vol. 24, 1981, pp. 159-164.
Patent Abstracts of Japan, JP 9-097832, Apr. 8, 1997.
U.S. Appl. No. 10/982,875, filed Nov. 8, 2004, Akiyama et al.
U.S. Appl. No. 11/408,087, filed Apr. 21, 2006, Akiyama.

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