Dielectric isolation type semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...

Reexamination Certificate

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C257S501000, C257SE29020

Reexamination Certificate

active

07417296

ABSTRACT:
A dielectric isolation type semiconductor device can achieve high dielectric resistance while preventing the dielectric strength thereof from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A drift N−region is bonded to a semiconductor substrate through a buried oxide film to from a high withstand-voltage device in the drift N−region. A first field plate is formed on the drift N−region in the vicinity of a drain electrode. A first high silicon concentration region composed of a buried N+region is formed in a porous oxide film region forming a part of the buried oxide film at a location right under the drain electrode. The drain electrode and the first field plate are electrically connected to the first high silicon concentration region through a drain N−well region.

REFERENCES:
patent: 5485030 (1996-01-01), Terashima
patent: 6025237 (2000-02-01), Choi
patent: 6049110 (2000-04-01), Koh
patent: 2004/0119132 (2004-06-01), Akiyama et al.
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patent: 3435930 (2003-08-01), None
Kazuo Imai, “A New Dielectric Isolation Method Using Porous Silicon”, Solid State Electronics, 1981, pp. 159-164, vol. 24, Pergamon Press Ltd., Great Britain.
French Office Action dated Feb. 19, 2007.

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