Dielectric isolation for high density semiconductor devices

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H01L 2704

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049656520

ABSTRACT:
A dielectrically isolated semiconductor device which is substantially planar can be manufactured. The structure is useable for integrated circuits wherein a significant savings in surface area can be obtained over prior techniques. The structure is particularly useful for bipolar integrated circuits wherein a semiconductor substrate with an epitaxial layer thereon contains a buried region partially in the substrate and in the epitaxial layer. The emitter and base regions are located in the epitaxial layer above the buried region. The dielectrically isolating region surrounds the emitter and base region at the surface and extends to a depth wherein it intersects with the buried region to fully isolate the device. The buried region is connected as the collector element of the transistor.

REFERENCES:
patent: 3386865 (1968-06-01), Doo
patent: 3534234 (1970-10-01), Clevenger
patent: 3615929 (1971-10-01), Portnoy et al.
patent: 3648125 (1972-03-01), Peltzer
Electronic Design 20, Sep. 26, 1968, pp. 64-65.
Jones et al., Electrochemical Technology, vol. 5, No. 5-6, May-Jun. 1967, pp. 308-310.
Doo et al., IBM Tech. Discl. Bull., vol. 8, No. 4, Sep. 1965, pp. 659-660.

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