Dielectric element isolated semiconductor device and a method of

Details Dielectric element isolated semiconductor device and a method of Dielectric element isolated semiconductor device and a method of

1995-01-11

1996-01-16

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257492, 257524, 257347, H01L 2704

Patent

active

054850304

ABSTRACT:
A high-breakdown voltage semiconductor device and a fabrication method are disclosed. A dielectric layer dielectrically isolates a semiconductor substrate from an n.sup.- type semiconductor layer. An n.sup.+ type semiconductor region having a lower resistance than the n.sup.+ type semiconductor layer is formed as if surrounded by a p.sup.+ type semiconductor region. The dielectric layer consists of a relatively thick first region and a relatively thin second region. The n.sup.+ type semiconductor region, which is located above the first region, occupies a narrower area than the first region. Thus, by forming the dielectric layer thick immediately under the first semiconductor layer and controlling the thickness of the dielectric layer at other potions, the breakdown voltage of the semiconductor device is improved without curbing RESURF effect.

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M. Yoshimo et al., "High Performance SOIMOSFET Using Ultra-thin SOI Film", IEDM87, pp. 640-643.

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