Dielectric deposition and cleaning process for improved gap fill

Details Dielectric deposition and cleaning process for improved gap fill Dielectric deposition and cleaning process for improved gap fill

1993-07-08

1995-06-20

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437228, H01L 2102

Patent

active

054260760

ABSTRACT:
A method of forming a silicon dioxide layer (SiO.sub.2) on a semiconductor substrate which fills gaps between surface features by means of applying, cleaning, and etching a series of layers of silicon dioxide. A layer of SiO.sub.2 is deposited by plasma enhanced chemical vapor deposition of tetraethyl orthosilicate; and a second layer of SiO.sub.2 is deposited thereon by thermal chemical vapor deposition. A series of etches are performed, removing the second layer of SiO.sub.2 from all regions of the substrates except the gaps. A third layer of SiO.sub.2, formed by plasma enhanced chemical vapor deposition, is then deposited. An additional etch step further planarizes the surface of the substrate.

REFERENCES:
Mehta, et al.; "A single-Pass, In-Situ Planarization Process Utilizing TEOS for Double-Poly, Double-Metal CMOS Technologies"; IEEE 6th Int'l VMIC Conf.; Jun. 1989, pp. 80-88.
Marks, et al.; "In Situ Planarization of Dielectric Surfaces Using Boron Oxide"; IEEE 6th Int'l VMIC Conf.; Jun. 1989; pp. 89-95.

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