1985-12-31
1987-12-15
Edlow, Martin H.
357 71, H01L 2934
Patent
active
047136820
ABSTRACT:
An integrated circuit comprising a substrate. The substrate comprises a semiconductor material and has a first surface. The circuit further comprises a layer of metalization interconnects over the first surface, each interconnect having a width. A first thin film layer comprising a dielectric barrier material is deposited directly onto the first layer of metalization interconnects. A second thin film layer comprising a dielectric passivating material is deposited directly onto the first thin layer of dielectric barrier material. A via is formed in the two thin film layers over a first metalization interconnect protruding into the via. The first metalization interconnect has a width less than the width of the via. A second metallization interconnect is connected to the first metalization interconnect in the via.
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Erie David G.
Lee Eddie C.
Roberts Jon A.
Edlow Martin H.
Honeywell Inc.
Prenty Mark
Udseth William
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