Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-10-24
2006-10-24
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S700000, C438S906000, C438S952000, C257SE21546
Reexamination Certificate
active
07125783
ABSTRACT:
A method for preventing the formation of watermark defects includes the steps of forming a pad oxide, a silicon nitride layer and a silicon oxynitride layer over a semiconductor substrate. A photoresist mask is formed over the resulting structure, with the silicon oxynitride layer being used as an anti-reflective coating during exposure of the photoresist material. An etch is performed through the photoresist mask, thereby forming a trench in the substrate. The photoresist mask is stripped, and the silicon oxynitride layer is conditioned. For example, the silicon oxynitride layer may be conditioned by a rapid thermal anneal in the presence of oxygen or nitrogen. A wet clean step is subsequently performed to remove a native oxide layer in the trench. The conditioned silicon oxynitride layer prevents the formation of watermarks during the wet clean process.
REFERENCES:
patent: 4693781 (1987-09-01), Leung et al.
patent: 5395790 (1995-03-01), Lur
patent: 5492858 (1996-02-01), Bose et al.
patent: 5541436 (1996-07-01), Kwong et al.
patent: 5956598 (1999-09-01), Huang et al.
patent: 6054393 (2000-04-01), Niccoli
patent: 6057208 (2000-05-01), Lin et al.
patent: 6103456 (2000-08-01), Tobben et al.
patent: 6129091 (2000-10-01), Lee et al.
patent: 6159823 (2000-12-01), Song et al.
patent: 6165854 (2000-12-01), Wu
patent: 6265283 (2001-07-01), Nariman et al.
patent: 6417070 (2002-07-01), Ballantine et al.
patent: 6444588 (2002-09-01), Holscher et al.
patent: 6541382 (2003-04-01), Cheng et al.
patent: 6930028 (2005-08-01), Hanratty et al.
patent: 2001/0026979 (2001-10-01), Chern
patent: 2002/0094593 (2002-07-01), Chiou et al.
Ghandhi S. “VLSI Fabrication Principles: Silicon and Gallium Arsenide”, 1983, John Wiley & Sons, Inc., p. 614.
Wolf S. “Silicon Processing for the VLSI-ERA: vol. 1-Process Technology”, 1986, Lattice Pr., vol. 1, p. 407, 476.
Lee et al., “Effects Of Post Annealing And Oxidation Processes On The Removal Of Damage Generated During The Shallow Trench Etch Process”, Jpn. J. Appl. Phys. vol. 37 (1998) Pt. 1, No. 12B; pp. 6916-6921.
Lee Shih-Ked
Lo Guo-Qiang
Mao Yu-Lung
Pan Ohm-Guo
Syau Tsengyou
Bever Hoffman & Harms
Fourson George
Integrated Device Technology Inc.
LandOfFree
Dielectric anti-reflective coating surface treatment to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dielectric anti-reflective coating surface treatment to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dielectric anti-reflective coating surface treatment to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3696338