Die stacking system and method

Details Die stacking system and method Die stacking system and method

2011-01-18

2011-01-18

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S778000

Reexamination Certificate

active

07872356

ABSTRACT:
Die stacking systems and methods are disclosed. In an embodiment, a die has a surface that includes a passivation area, at least one conductive bond pad area, and a conductive stacked die receiving area sized to receive at least a second die.

REFERENCES:
patent: 7034388 (2006-04-01), Yang et al.
patent: 7095105 (2006-08-01), Cherukuri et al.
patent: 7218006 (2007-05-01), Kang et al.
patent: 7279795 (2007-10-01), Periaman et al.
patent: 2004/0115867 (2004-06-01), Shibata
patent: 2005034238 (2005-04-01), None
patent: 2007000697 (2007-01-01), None
International Search Report—PCT/US2008/063993, International Searching Authority—European Patent Office—Sep. 2, 2008.
Written Opinion—PCT/US2008/063993, International Searching Authority—European Patent Office—Sep. 2, 2008.

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