Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2006-01-12
2008-11-25
Andújar, Leonardo (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S620000
Reexamination Certificate
active
07456507
ABSTRACT:
A seal ring structure between an integrated circuit region and a scribe line is provided. In one embodiment, the seal ring structure comprises a substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; a first passivation layer formed over the plurality of layers of metal lines, the first passivation layer having an opening therein exposing a portion of a top metal line; residual metal pad layers formed proximal the opening of the first passivation layer; and a second passivation layer formed over the first passivation layer, the second passivation layer enveloping the exposed residual metal pad or metal redistribution layers and further having a trench above the top metal line.
REFERENCES:
patent: 2004/0150070 (2004-08-01), Okada et al.
patent: 1542505 (2004-11-01), None
Andújar Leonardo
Birch & Stewart Kolasch & Birch, LLP
Taiwan Semiconductor Manufacturing Co. Ltd.
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