Seal for a joint or juncture – Seal between fixed parts or static contact against... – Contact seal for other than internal combustion engine – or...
Reexamination Certificate
1999-11-24
2002-07-02
Browne, Lynne H. (Department: 3626)
Seal for a joint or juncture
Seal between fixed parts or static contact against...
Contact seal for other than internal combustion engine, or...
C277S654000, C277S919000, C438S462000, C438S672000
Reexamination Certificate
active
06412786
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to packaging fabrication, and, more particularly, to a seal ring that is located around a die for preventing the internal circuit of the die from later stress induced during the period of cutting wafers.
2. Description of the Prior Art
In the semiconductor process, a plurality of dies, each of which contains an integrated circuit (IC), are fabricated on a semiconductor wafer at a single time. Scribe lines are provided between every two adjacent dies so that these dies can be separated by cutting the semiconductor wafer along these scribe lines. However, when a wafer is cut into a plurality of dies, lateral stress is induced, thereby affecting the internal circuits via the structure of the IC.
One approach for solving such a problem is to form a die seal ring between the scribe line and the peripheral region of the internal circuit. Therefore, stress induced by cutting wafers is generally blocked by the die seal ring and will not directly affect the internal circuit of a die.
FIG. 1
shows a top view of a die. It should be noticed that all subsequent figures are not to scale. As
FIG. 1
shows, each die
10
is separated from other die
10
by scribe lines
12
, and each die
10
is encompassed by one die seal ring
14
. With respect to die seal ring
14
, a stacked structure comprising metal rings and dielectric layers, this component is usually formed together with die
10
in the multi-metal interconnection process.
FIG. 2
(prior art) qualitatively illustrates a cross-sectional view of conventional die seal structure. Herein, the illustrated example is a die seal ring with a triple-metal interconnection. Now referring to
FIG. 2
, the whole structure is formed on substrate
20
, and isolation
21
is used to separate the die seal ring and internal circuit (chip), such as die
10
. Die seal ring comprises first dielectric layer
22
, second dielectric layer
23
, third dielectric layer
24
and fourth dielectric layer
25
, wherein second dielectric layer
23
is located on first dielectric layer
22
, third dielectric layer
24
is formed on second dielectric layer
23
and fourth dielectric layer
25
is the uppermost layer.
Metal rings
26
and
28
locate on dielectric layer
22
,
23
and
24
, respectively. And metal plugs
295
are located between these metal rings. Moreover, metal plugs
295
also are used to connect these blocks to substrate
20
and then any charger appear in these metal rings and metal plugs
295
are short to a ground point. Finally, passivation
29
is formed and covers all these dielectric layers and all these metal rings. In summary, conventional die seal ring shown in
FIG. 2
is produced by alternately forming these dielectric layers and these metal rings by common semiconductor process and do not require extra steps. Moreover, these metal rings and metal plugs
295
are also formed during the common metallization and plug process and do not require extra steps. Such a die seal ring is utilized to enhance robustness to sawing stress, thereby preventing the internal circuit from relative damage.
As shown in
FIG. 2
, because the net height of the conventional die seal ring is directly proportional to the summation of heights of all metal rings, it is clear that the net weight is large as height of any metal ring is large or number of metal rings is increased. Owing to the truth that die
10
is surrounded by die seal ring
14
and then any layer formed on die
10
also is contiguous to die seal ring
14
, and usually upper layers are dielectric layers such as passivation layers that with a viscosity. Therefore, it is obvious that surface of die
10
is not planar, even when a planarizing process had been executed.
Significantly, when die
10
only includes elements that will not interact with external light, such as memory cells, the uneven surface of die
10
will not induce any disadvantage. But when die
10
comprises photodetector pixel cell that is used to detect external light which will propagate through these upper layers, the uneven surface will induce an issue that sensitivities of different pixel cells is different if they are located on different part of die
10
, and then the quality of die
10
is degraded.
Accordingly, it is clear that conventional die seal ring will induce the issue of uneveness of the surface of the die, and then it is desired to develop a die seal ring that efficiently prevents this issue.
SUMMARY OF THE INVENTION
The primary object of the present invention is to propose a new structure for a of die seal ring.
A further object of the present invention is to propose a die seal ring that efficiently prevents surface transmutation of the surrounding chip.
Moreover, a specific object is to propose a manufacturable die seal ring, regardless of structure of fabricating process of the proposed die seal ring.
In order to achieve these objects, the present invention proposes a die seal ring as an embodiment. The embodiment is formed on a substrate and can be used to both prevent lateral stress, which may damage the internal circuit in a due, and prevent the height of die seal ring from becoming too large to damage the smoothness of the enclosed integrated circuit.
Moreover, the provided die seal ring comprises a plurality of dielectric layers and a plurality of metal structures, wherein any metal structure is not overlapped with other metal structures. Dielectric layers are located on substrate in sequence, and each metal structure is stacked by one metal ring and one metal plug. Herein, any metal ring is located on a dielectric layer and is covered by another dielectric layer, and metal rings of different metal structures are located on different dielectric layers. Further, any metal plug is located in the dielectric layers and is used to connect the metal ring to the substrate. Of course, if the aspect ratio of any metal plug is too large to be properly formed, an appendant metal ring is used to reduce the aspect ration of the metal plug.
Significantly, because any metal ring can directly connect to the substrate without application of other metal ring except for its aspect ration being too large, the height of any metal structure can be efficiently reduced and then the height of the presented seal ring also can be efficiently reduced.
REFERENCES:
patent: 3968193 (1976-07-01), Langston, Jr. et al.
patent: 4363076 (1982-12-01), McIver
patent: 4700473 (1987-10-01), Freyman et al.
patent: 5891808 (1999-04-01), Chang et al.
patent: 5907788 (1999-05-01), Kasai
patent: 5918123 (1999-06-01), Yang
patent: 5966634 (1999-10-01), Inohara et al.
patent: 5970346 (1999-10-01), Liaw
patent: 5972788 (1999-10-01), Ryan et al.
patent: 6043115 (2000-03-01), Pan
patent: 6100118 (2000-08-01), Shih et al.
patent: 6162686 (2000-12-01), Huang et al.
Browne Lynne H.
Moga, Esq. Thomas T.
Pickard Alison K.
Powell Goldstein Frazer & Murphy LLP
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