Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2001-11-30
2003-05-20
Flynn, Nathan J. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S618000, C257S626000, C257S640000, C257S632000, C257S629000, C257S649000, C257S635000, C257S760000, C257S758000, C257S701000
Reexamination Certificate
active
06566736
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly to die seal structures and methods for protecting semiconductor devices from moisture.
BACKGROUND OF THE INVENTION
Semiconductor devices, such as integrated circuits (ICs), are typically manufactured by forming multiple devices and interconnections (e.g., circuits) on a semiconductor wafer, which are then separated into individual parts or dies. Individual devices are located within corresponding die areas on the wafer with sufficient spacing provided between adjacent devices for subsequent separation operations and the manufacturing tolerances associated therewith. Typically, the devices are oriented in grid style on the wafer, with rows and columns of devices located on the top or front side of the wafer. The devices are formed using multi-step processing involving selective deposition, removal, and/or doping of active regions on the wafer surface to build electrical components (e.g., memory cells, transistors, diodes, resistors, capacitors, etc.) and connections therebetween. Within a particular die area, many electrical components are thus formed, and are interconnected with one another using one or more overlying metal layers, by which an integrated circuit device is produced. Thereafter, the individual dies or devices are separated from the wafer.
Following die separation, individual dies may then be assembled into integrated circuit chips. In constructing an integrated circuit chip, a semiconductor die is mounted onto a lead frame and wires are connected between lead frame leads and corresponding bonding pads on the die using a technique known as wire bonding. Wire bonding involves attachment of fine aluminum or gold wires to the die bonding pads through various bonding techniques, such as thermocompression bonding or ultrasonic bonding. Once the pads on the die are appropriately connected to the lead frame leads, the lead frame is encapsulated in a ceramic or plastic package, which may then be assembled onto a printer circuit board (PCB) by soldering the exposed portions of the leads onto corresponding conductive pads on the board. Alternatively, the dies may be mounted directly onto PCBs, where electrical connections are made between conductive circuit board pads and electrically conductive bonding pads on the dies. In this regard, Flip-Chip technology has recently become popular, wherein an individual semiconductor die is mounted directly to a circuit board. Bumps (e.g., solder bumps, plated bumps, gold stud bumps, adhesive bumps, or the like) are added to the bonding pads of the die using a process known as bumping. With stud bumps attached, the die or chip is then “flipped” over, with the bonding pads facing downward, and the bumps are attached to corresponding pads on the PCB using, for example, ultrasonic or other bonding techniques.
Moisture is known to cause adverse effects in the operational reliability and/or longevity of semiconductor devices. For example, where the electrical components within an active region of a semiconductor die are exposed to moisture, the characteristics of the transistors, memory cells, or the like may be affected. Thus, in a flash memory device, for instance, internal exposure to such moisture may change the programmed and/or erased threshold voltages associated with one or more memory cell structures therein, resulting in reduced reliability for storing or providing access to user data. During semiconductor device fabrication, as well as during subsequent bonding, packaging, and eventual operation of the device die (e.g., mounted in an integrated circuit package or directly on a circuit board), the exterior of the die may be exposed to a moist ambient operating environment. Where such moisture invades the electrical component areas of the device, operational degradation may result. It is therefore desirable to prevent or reduce the likelihood of such moisture entering the interior active regions of the device die, both during manufacturing and thereafter.
Various attempts have previously been made to seal the interior of the semiconductor device dies from such ambient moisture. The bottom substrate in most semiconductor devices (e.g., silicon) effectively blocks moisture from entering the interior of the die from the bottom, but materials commonly employed in fabricating further layers above the substrate provide a path for moisture to enter from the top and/or sides of the die following die separation. For example, certain commonly employed insulator materials such as silicon oxide (SiO) are relatively easily penetrated by moisture. Accordingly, lateral or side seal structures are often provided between the die edges and the active region. Such side seal structures are formed in one or more layers in the processed semiconductor device using vertically oriented contacts (e.g., such as tungsten) and metal die seal structures, wherein the contacts and die seal metal structures extend around the periphery of the active region of each individual die.
Each layer formed between the bottom substrate and the upper most metal layer typically includes such a structure, by which a vertical moisture barrier extends laterally around the periphery of the device active region from the bottom substrate to the upper most metal layer. Thus, where multiple metal connection layers are employed in a device fabrication process, the lower most die seal contacts extend from the substrate to a metal die seal structure in the first metal layer. Additional contacts are formed in an overlying insulator material, which extend upward from the metal die seal structure in the first metal layer to a similar seal structure in the second metal layer. This structure is then repeated for each successive metal layer until the final metal layer is formed.
In the past, moisture has been prevented from entering the die active region by an upper seal or liner layer directly overlying the upper most metal layer. A final insulator layer, such as SiO is then formed over the liner. Openings are made (e.g., etched) in the liner and final insulator layers so as to expose die bonding pads in the upper most metal layer for wire bonding after die separation. Thus, in the interior of the active region, the liner layer and the exposed metal bonding pads provide a seal against moisture entering from the top of the die. Furthermore, because the liner layer is formed directly over the final metal layer, a moisture seal is provided at the peripheral edges of the active region, where the liner layer is formed directly over the metal die seal structure in the top metal layer. Thus, although moisture may pass from the top ambient through the upper most SiO insulator layer, the liner layer prevents further downward moisture transfer to the electrical components below.
However, the use of such a liner overlying the upper metal layer may cause problems in the operation of the circuitry in the semiconductor device. For instance, in order to satisfy the demand for more and more functionality in modern semiconductor products, there is a continuing trend toward higher device densities. Such higher device densities, in turn, are facilitated by reduction in the device dimensions achieved through smaller and smaller features sizes. These feature sizes include the width and spacing of interconnecting lines in the various metal layers, which have recently become smaller to the point where electrical characteristics of the liner layer overlying the upper most metal layer features may have an adverse effect on the device performance. Thus, there is a need for improved moisture sealing structures and methodologies by which the semiconductor device and the components therein can be protected from moisture, without adversely affecting the circuit operation.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention, and is intended neither to
Ogawa Hiroyuki
Sun Yu
Wu Yider
Advanced Micro Devices , Inc.
Eschweiler & Associates LLC
Flynn Nathan J.
Greene Pershelle
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