Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Shift direction control
Reexamination Certificate
2001-08-02
2002-12-10
Tokar, Michael (Department: 2819)
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
Shift direction control
C377S077000, C377S078000, C377S080000, C326S016000, C326S046000, C326S113000, C327S525000, C714S724000, C714S725000
Reexamination Certificate
active
06493414
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to techniques for providing various information parameters stored on an integrated circuit die.
2. Prior Art
Certain information is of great assistance to process/design engineers for enhancing performance of an integrated-circuit manufacturing process. This information includes various parameters for a particular die or a packaged part. These parameters include, but are not limited to, the following: lot number; wafer number; wafer row number; wafer column number; row fuse number blown for redundancy, if any; column fuse number blown for redundancy, if any; etc. A need exists for a technique for storing various parameters to assist process and design engineers in improving a particular fabrication process.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a system and a method for storing and presenting various parameters related to an integrated-circuit chip.
A number of fuses are connected through electrical links provided by a CMOS transmission gate to respective input terminals of a multi-bit serial shift register. The output of the serial shift register is connected through a multiplexer to an output buffer. When the chip is not in test mode (TM=0), the fuses are electrically connected to respective input terminals of the shift register, and the output of the serial shift register is electrically isolated from the output buffer.
When the chip is in test mode, the electrical links between the fuses and the shift register bits are open leaving the fuse information isolated in the shift register. The test mode also connects the output of the shift register to the output buffer through the multiplexer so the output of the first shift register cell is provided on the output pin of the output buffer. The rest of the shift register information is serially shifted out by toggling a CET pin with thirty one negative edges of a positive-logic CET signal.
The present invention is for a system and method that provides a serial bit sequence that represents one or more information parameters stored in an integrated-circuit chip. The system includes a plurality of fuse modules, each having a fuse that is blown or not blown to represent a respective bit of the serial bit sequence at an output terminal of each fuse module. A parallel-load/serial-shift shift-register has a number of serially-connectable bit storage cells and a shift-register output terminal. Each bit storage cell has a bit-cell data input terminal and a bit-cell data output terminal. Each bit cell stores a respective bit of the serial bit sequence provided by a fuse module.
Each of the bit storage cells has a respective fuse-input transmission gate that has an input terminal coupled to an output terminal of a respective one of the plurality of fuse modules. Each of the bit storage cells also has an output terminal coupled to a an input terminal of an adjacent bit storage cell. The fuse-input transmission gate is controlled by a TEST MODE (TM) signal to provide parallel loading of the bit storage cells of the shift register with the bits of the bit sequence from the fuse modules.
Assume that the bits of the shift register are stored so that higher-ordered bits are first shifted out of the register. Each of the bit storage cells, except for the starting shift register bit cell, also has a serial-data transmission gate that has an input terminal coupled to an output terminal of an adjacent lower-order one-bit storage cell and that has an output terminal coupled to a respective bit storage cell data input terminal of a higher-order bit storage cell. The respective transmission gates are controlled by a SHIFT signal to serially connect the bit storage cells together to provide for serially shifting data through adjacent cells of the shift register to the output terminal of the shift register.
A two-input data selector and buffer has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to an output terminal of a memory array for storing normal-data in the integrated-circuit chip. The second input terminal is coupled to the data output terminal of the parallel-load/serial-shift shift-register. The two-input data selector and buffer has a control terminal that controls connection between the multiplexer output terminal and either the first input terminal or the second input terminal.
The system in a test mode has the respective fuse-input transmission gates off, the respective serial-data transmission gates on, and the two-input data selector and buffer provides data at its output terminal from the shift-register.
The system in a non-test mode has the respective fuse-input transmission gates on, the respective serial-data transmission gates are off, and the two-input data selector and buffer provides normal data at its output terminal.
The present invention also includes a method for providing a serial bit sequence that represents one or more information parameters stored on an integrated-circuit chip. The method includes the steps of: storing each respective bit of the serial bit sequence in a respective ones of a plurality of fuse modules by blowing or not blowing a fuse in each of the plurality of fuse modules; connecting output terminals of the fuse modules to respective input terminals of one of a plurality of serially-connectable bit storage cells of a parallel-load/serial-shift shift-register; parallel loading through a fuse-input transmission gate respective ones of the bit storage cells of the shift register with a bit from a respective one of the fuses. Each of the bit storage cells has a respective fuse-input transmission gate that has an input terminal coupled to an output terminal of a respective one of the plurality of fuse modules and that has an output terminal coupled to a respective bit storage cell data input terminal, wherein the serial data transmission gate provides for serially shifting data through an adjacent cell of the shift register to the output terminal of the shift register. Each of the bit storage cells, except for the starting shift register bit cell, also has a serial-data transmission gate that has an input terminal coupled to an output terminal of an adjacent lower-order one-bit storage cell and that has an output terminal coupled to a respective bit storage cell data input terminal of a higher-order bit storage cell, wherein the respective transmission gates serially connect the bit storage cells to provide for serially shifting data through adjacent cell of the shift register to the output terminal of the shift register.
REFERENCES:
patent: 3829713 (1974-08-01), Canning
patent: 5572536 (1996-11-01), Thiruvengadam
patent: 6301322 (2000-10-01), Manning
patent: 6346822 (2002-02-01), Nishikawa
King Patrick T.
Nanoamp Solutions, INC
Tan Vibol
Tokar Michael
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