Die-in-heat spreader microelectronic package

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support

Reexamination Certificate

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Details

C257S675000

Reexamination Certificate

active

06709898

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and processes for packaging microelectronic dice. In particular, the present invention relates to a packaging technology that encapsulates a microelectronic die within a heat spreader.
2. State of the Art
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As these goals are achieved, microelectronic dice become smaller. Of course, the goal of greater packaging density requires that the entire microelectronic die package be equal to or only slightly larger (about 10% to 30%) than the size of the microelectronic die itself. Such microelectronic die packaging is called a “chip scale packaging” or “CSP”.
As shown in
FIG. 27
, true CSP would involve fabricating build-up layers directly on an active surface
204
of a microelectronic die
202
. The build-up layers may include a dielectric layer
206
disposed on the active surface
204
and conductive traces
208
may be formed on the dielectric layer
206
, wherein a portion of each conductive trace
208
contacts at least one contact
212
on the active surface
204
. External contacts, such as solder balls or pins for contacting an external devices (not shown), may be fabricated to contact at least one conductive trace
208
.
FIG. 27
illustrates the external contacts as solder balls
214
which are surrounded by a solder mask material
216
on the dielectric layer
206
. However, the surface area provided by the active surface
204
generally does not provide enough surface for all of the external contacts needed to contact the external device (not shown) for certain types of microelectronic dice (e.g., logic).
Additional surface area can be provided with the use of an interposer, such as a substantially rigid material or a substantially flexible material.
FIG. 28
illustrates a substrate interposer
222
having a microelectronic die
224
attached to and in electrical contact with a first surface
226
of the substrate interposer
222
through solder balls
228
. The solder balls
228
extend between contacts
232
on the microelectronic die
224
and conductive traces
234
on the substrate interposer first surface
226
. The conductive traces
234
are in discrete electrical contact with bond pads
236
on a second surface
238
of the substrate interposer
222
through vias
242
that extend through the substrate interposer
222
. External contacts
244
are formed on bond pads
236
. The external contacts
244
are utilized to achieve electrical communication between the microelectronic die
224
and an external electrical system (not shown).
The use of the substrate interposer
222
requires number of processing steps which increase the cost of the package. Additionally, the use of the small solder balls
228
presents crowding problems which can result in shorting between the small solder balls
228
and can present difficulties in inserting underfill material between the microelectronic die
224
and the substrate interposer
222
to prevent contamination and provide mechanical stability. Furthermore, the necessity of having two sets of solder balls (i.e., small solder balls
228
and external contacts
244
) to achieve connection between the microelectronic die
224
and the external electrical system decreases the overall performance of the package.
Another problem arising from the fabrication of a smaller microelectronic die is that the density of power consumption of the integrated circuit components in the microelectronic die has increased, which, in turn, increases the average junction temperature of the die. If the temperature of the microelectronic die becomes too high, the integrated circuits of the semiconductor die may be damaged or destroyed. Furthermore, for microelectronic dice of equivalent size, the overall power increases which presents the same problem of increased power density.
Various apparatus and techniques have been used for removing heat from microelectronic dice. One such heat dissipation technique involves the attachment of a heat sink to a microelectronic die.
FIG. 29
illustrates an assembly
250
comprising a microelectronic die
252
physically and electrically attached to a substrate carrier
254
by a plurality of solder balls
256
. A heat sink
258
is attached to a back surface
262
of the microelectronic die
252
by a thermally conductive adhesive
264
. The heat sink
258
is usually a slug constructed from a thermally conductive material, such as copper, copper alloys, aluminum, aluminum alloys, and the like. Heat generated by the microelectronic die
252
is conductively drawn into the slug-type heat sink
258
(following the path of least thermal resistance) and convectively dissipated from the slug-type heat sink
258
into the air surrounding the heat sink assembly
250
. Thus, as the size or “footprint” of microelectronic dice decreases, the contact area between the micro-electronic die
252
and the heat sink
258
decreases, which reduces the area available for conductive heat transfer. Thus, with a decrease of the size in the microelectronic die
252
, heat dissipation from a slug-type heat sink
258
becomes less efficient.
Therefore, it would be advantageous to develop new apparatus and techniques to provide additional surface area to form traces for use in CSP applications, eliminate the necessity of the substrate interposer, and provide improved heat dissipation.


REFERENCES:
patent: 4400870 (1983-08-01), Islam
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5409865 (1995-04-01), Karnezos
patent: 5422513 (1995-06-01), Marcinkiewicz et al.
patent: 5497033 (1996-03-01), Fillion et al.
patent: 5527741 (1996-06-01), Cole et al.
patent: 5703400 (1997-12-01), Wojnarowski et al.
patent: 5745984 (1998-05-01), Cole, Jr. et al.
patent: 6271469 (2001-08-01), Ma et al.
patent: 6274391 (2001-08-01), Wachtler et al.
patent: 6380615 (2002-04-01), Park et al.
patent: 6396136 (2002-05-01), Kalidas et al.
patent: 6423570 (2002-07-01), Ma et al.
patent: 11045955 (1999-02-01), None
patent: 11312868 (1999-11-01), None
IBM Technical Disclosure Bulletin, p. 4469-4470, Mar. 1980.*
IBM Technical Disclosure Bulletin, p. 4469-4470, Mar. 1980.

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