Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2001-12-05
2003-09-23
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S113000, C438S459000, C438S464000, C414S935000
Reexamination Certificate
active
06624048
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit fabricating. More particularly, this invention relates to back grinding individual integrated circuits after the integrated circuits are diced from the substrate on which they are fabricated.
BACKGROUND
Integrated circuits are typically fabricated on substrates containing a large number of individual integrated circuits. The fabrication process typically involves a number of processing steps such as deposition steps and etching steps to which the substrate is subjected to fabricate the integrated circuits. Each additional fabricating step used to process the substrate and construct the integrated circuits adds additional costs that increase the total cost of the finished integrated circuit. In addition, each fabricating step introduces the possibility of additional defects to the integrated circuit. These defects tend to decrease the yield of the fabrication process, and thus also increase the cost of the final integrated circuit. In today's highly competitive integrated circuit market, a seemingly small difference between the costs of two different integrated circuits can be the difference between a successful product and an unsuccessful product.
For example, the substrates on which the integrated circuits are formed are typically thinned prior to dicing and removal of the individual integrated circuits from the substrate. This process is generally referred to as substrate back side grinding. Unfortunately, as substrates become increasingly larger, and desired integrated circuit thicknesses become increasingly thinner, it becomes ever more difficult to control the back side grinding process. Further, the thinned substrates are much more delicate than the unthinned substrates, and thus tend to break more easily. Additionally, as some of the integrated circuits on the substrate do not function properly, not all of the integrated circuits need to be thinned.
Therefore, what is needed is a method that tends to streamline the fabrication process and produces an increased yield as compared to prior art fabricating processes.
SUMMARY
The above and other needs are met by a method for fabricating integrated circuits, where a plurality of individual integrated circuits are fabricated on a substrate. The substrate is partitioned into portions, and the partitioned portions of the substrate are individually back ground. In a most preferred embodiment, the partitioned portions of the substrate are individual integrated circuits.
Polishing or back grinding the individual integrated circuits after the substrate has been cut or diced as described in the above embodiment affords a number of advantages over the prior art. For example, polishing the individual circuits after they have been removed from the substrate ensures that only those portions of the substrate that will actually be used are polished. In additions by polishing the integrated circuits individually, the polishing process can be more accurately controlled to ensure that each individual integrated circuit has been polished appropriately. Polishing the individual integrated circuits after they have been cut from the substrate also minimizes the need to handle a relatively thin and delicate substrate during and after the polishing process, and thereby minimizes the likelihood that the substrate will be damaged.
In another embodiment there is provided an apparatus for processing integrated circuits having front sides and back sides. A picker engages the front side of one of the integrated circuits and removes the integrated circuit from a diced substrate. A grinder grinds the back side of the integrated circuit while it is held by the picker. A placer places the back ground integrated circuit in a desired location. For example, the picker may be a device such as an extendable shaft that engages the integrated circuit. The placer then translates the picker from station to station, such as from the location of the diced substrate, to the grinder location, and then to a package.
The above described apparatus provides many of the same advantages as the previously described method for fabricating integrated circuits. By polishing the integrated circuits after they have been separated from the substrate, the apparatus minimizes the need to handle the delicate substrate, and thus minimizes the likelihood that the substrate will be damaged. In addition, grinding each of the integrated circuits individually allows the grinding process to be more accurately controlled and custom tailored to each individual integrated circuit. The grinder is preferably incorporated into the processing apparatus, thereby eliminating the need to move the substrate to and from a remote location. Finally, only grinding the desired integrated circuits eliminates the need to polish portions of the substrate that will not actually be used. Further, if so desired, the different integrated circuits can be polished to varying degrees. Therefore, the embodiment of the present invention described above provides a number of benefits over the prior art.
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patent: 5273940 (1993-12-01), Sanders
patent: 5399233 (1995-03-01), Murazumi et al.
patent: 5989939 (1999-11-01), Fjelstad
patent: 6060373 (2000-05-01), Saitoh
patent: 6162701 (2000-12-01), Usami et al.
patent: 6294439 (2001-09-01), Sasaki et al.
patent: 6420209 (2002-07-01), Siniaguine
LSI Logic Corporation
Luedeka Neely & Graham
Picardat Kevin M.
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