Die architecture accommodating high-speed semiconductor devices

Details Die architecture accommodating high-speed semiconductor devices Die architecture accommodating high-speed semiconductor devices

1999-11-12

2000-11-07

Mai, Son

Static information storage and retrieval

Format or disposition of elements

356 63, 257692, 257786, G11C 502, H01L 2348

Patent

active

061445754

ABSTRACT:
In a semiconductor memory device, a die architecture is provided that arranges memory arrays into a long, narrow configuration. Bond pads may then be placed along a long side of a correspondingly shaped die. As a result, this architecture is compatible with short lead frame "fingers" for use with wide data busses as part of high speed, multiple band memory integrated circuits.

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