Die architecture accommodating high-speed semiconductor devices

Details Die architecture accommodating high-speed semiconductor devices Die architecture accommodating high-speed semiconductor devices

1998-02-13

1999-08-10

Mai, Son

Static information storage and retrieval

Format or disposition of elements

365 63, 257692, 257786, G11C 502

Patent

active

059368772

ABSTRACT:
In a semiconductor memory device, a die architecture is provided that arranges memory arrays into a long, narrow configuration. Bond pads may then be placed along a long side of a correspondingly shaped die. As a result, this architecture is compatible with short lead frame "fingers" for use with wide data busses as part of high speed, multiple band memory integrated circuits.

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patent: 5231607 (1993-07-01), Yoshida et al.
patent: 5293334 (1994-03-01), Shimizu
patent: 5408129 (1995-04-01), Farmwald et al.

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