Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2000-12-21
2003-03-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S462000
Reexamination Certificate
active
06528392
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field and pertains, more specifically, to an apparatus for separating a semiconductor component, such as a semiconductor chip from a semiconductor wafer. The dicing separation is effected along a scribe line. An insulating layer is provided on the semiconductor wafer, in which a number of metallization planes are formed. A top metallization plane is electrically connected to an underlying metallization plane via a connecting hole.
Semiconductor components are usually separated from a wafer by sawing along a scribe line which establishes the boundaries between the individual semiconductor chips in the semiconductor wafer. The separation is referred to as “dicing.” Sawing the semiconductor wafer apart must be done in such a manner that cracking in the individual semiconductor components is reliably prevented.
An apparatus is described in published European patent application EP 0 806 795 A2, in which, in order to prevent cracking in an insulating layer during the separation of a semiconductor component from a wafer along a scribe line in the insulating layer, a number of metallization planes is formed, a top metallization plane of which is electrically connected to an underlying metallization plane via a connecting layer in a connecting hole. The configuration described in the preceding introductory text is thus known from that publication.
Semiconductor components, such as, in particular, memory chips, often contain fuses which are situated in the transition area between the semiconductor chip and the scribe line and store information which is needed at wafer level but can be omitted after the semiconductor wafer has been sawn apart. For this reason, these fuses are preferably accommodated in the sawing edge or the kerf of the individual semiconductor chips on both sides of the scribe line. Such fuses often consist of polycrystalline silicon which is caused to melt by currents above a certain current intensity. These so-called “polyfuses” have previously been provided by etching fuse windows into the kerf of the semiconductor chips. As a result, the layer thickness of the insulating layer, i.e. especially of the silicon dioxide layer on the semiconductor wafer, is here reduced which considerably facilitates the sawing-apart of the semiconductor wafer.
For some time, however, polyfuses have been increasingly replaced by metal fuses which are formed, for example, by vapor deposition of thin metal films on an insulating base. These metal fuses are situated distinctly higher than the previous polyfuses and are arranged above the so-called “polylevel.” Polycrystalline silicon filling structures are also frequently introduced in the transition area between semiconductor chip and scribe line in order to create surfaces here which are as level as possible.
Both measures, namely, on the one hand, the increasing use of metal fuses and, on the other hand, the use of polycrystalline silicon filling structures, lead to the insulating layer being made much thicker than previously in the transition area between the semiconductor chip and the scribe line, i.e. in the kerf, which makes separating the individual semiconductor chips, by sawing, from the semiconductor wafer along the scribe line much more difficult. In consequence, the yield of semiconductor components is reduced since numerous semiconductor components become useless due to cracking because the sawing has become much more difficult.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a dicing configuration for separating a semiconductor component from a semiconductor wafer along a scribe line which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which reliably avoids cracking during the sawing-apart of the semiconductor wafer in a simple manner.
With the above and other objects in view there is provided, in accordance with the invention, a dicing configuration for separating a semiconductor component from a semiconductor wafer along a scribe line, wherein an insulating layer is formed on the semiconductor wafer, and a number of metallization planes are formed in the insulation layer, with a top metallization plane electrically connected to an underlying metallization plane via a connecting layer in a connecting hole formed in the insulation layer. The insulating layer is formed with an additional recess together with the connecting hole, for thinning the insulating layer in a transition area between the semiconductor component and the scribe line.
In other words, in the configuration of the type initially mentioned there is provided an additional recess, which is introduced together with the connecting hole, for thinning the insulating layer in the transition area between the semiconductor chip and the scribe line.
In the arrangement according to the invention, the step for forming a connection between the top metallization plane and the underlying metallization plane, which is necessary in any case, is used for making the insulating layer thinner in the transition area between the semiconductor chip and the scribe line which then considerably facilitates sawing the semiconductor wafer apart into the individual semiconductor chips.
In accordance with an added feature of the invention, only the insulating layer is provided on the semiconductor body in a region of the additional recess between the semiconductor body and the scribe line.
In accordance with an additional feature of the invention, the transition area is approximately 3 &mgr;m wide.
In accordance with a concomitant feature of the invention, there are formed a plurality of recesses in the insulating layer for thinning the insulation layer in the transition area.
There is also provided a dicing method for separating a semiconductor component from a semiconductor wafer along a scribe line, which comprises:
forming a first metallization plane on a semiconductor wafer;
depositing an insulating layer on the semiconductor wafer and on the first metallization plane;
forming a connecting hole in the insulating layer down to the first metallization plane and simultaneously forming an additional recess in the insulating layer for thinning the insulating layer in a transition area between the connecting hole and a scribe line;
depositing a plurality of metallization planes in the insulation layer, with a top metallization plane electrically connected to the first metallization plane via a connecting layer in the connecting hole; and
separating the semiconductor component from the semiconductor wafer along the scribe line.
In addition, only the insulating layer is provided on the semiconductor body in the transition area between the semiconductor chip and the scribe line so that there is no polycrystalline silicon filling structures there. This measure, too, furthers simpler sawing-apart of the semiconductor wafer into the individual semiconductor chips.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an dicing configuration for separating a semiconductor chip from a semiconductor wafer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 3798135 (1974-03-01), Bracken
patent: 5136354 (1992-08-01), Morita et al.
patent: 5593925 (1997-01-01), Yamaha
patent: 5899729 (1999-05-01), Lee
patent: 5943591 (1999-08-01), Vokoun et al.
patent: 5998282 (1999-12-01), Likaszek
patent: 6022792 (2000-02-01), Ishii
patent: 0 806 795 (1997-11-01), None
Feurle Robert
Savignac Dominique
Niebling John F.
Stevenson André C
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