Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2008-01-29
2008-01-29
Nguyen, Cuong (Department: 2811)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S142000, C438S224000, C438S228000
Reexamination Certificate
active
11799496
ABSTRACT:
Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.
REFERENCES:
patent: 5447876 (1995-09-01), Moyer et al.
patent: 6048746 (2000-04-01), Burr
patent: 6087892 (2000-07-01), Burr
patent: 6091283 (2000-07-01), Murgula et al.
patent: 6169310 (2001-01-01), Kalnitsky et al.
patent: 6218708 (2001-04-01), Burr
patent: 6218895 (2001-04-01), De et al.
patent: 6303444 (2001-10-01), Burr
patent: 6489224 (2002-12-01), Burr
patent: 6617656 (2003-09-01), Lee et al.
patent: 6677643 (2004-01-01), Iwamoto et al.
patent: 6936898 (2005-08-01), Pelham et al.
patent: 7049699 (2006-05-01), Masleid et al.
patent: 0624909 (1994-11-01), None
Burr James B.
Pelham Mike
Nguyen Cuong
Transmeta Corporation
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