Excavating
Patent
1983-05-09
1986-02-04
Fleming, Michael R.
Excavating
371 16, G06F 1100
Patent
active
045690499
ABSTRACT:
A central processor unit sends known simulated data signals to the video display subsystem and disk storage subsystem of a computer system; the simulated data is processed by the subsystems as if it were real data and is then returned to the processor. The processed signals or their error detecting codes are compared with the corresponding information expected to be returned and an error is signalled if the returned signals differ from those expected. During the diagnostic routine, the video display is blanked and the video character generator is slowed down. In response to a known sequence of character information supplied thereto, the character generator supplies a corresponding slowed-down stream of bits representing the resulting video; this stream of bits is fed to a slow speed serial port and then to the processor, where an error detecting code is generated from the bit stream and compared to an error detecting code provided by the character generator in response to the input thereto. Similarly, a known data sequence is provided to the disk subsystem where it is treated as if it were data read from the read/write head of the disk drive; for this purpose, the sequence is reversed in order prior to being processed as simulated read data.
REFERENCES:
patent: 3222651 (1965-12-01), Fabiszewski et al.
patent: 3787815 (1974-01-01), Farr
patent: 4223382 (1980-09-01), Thorsrub
patent: 4327408 (1982-04-01), Frissell et al.
patent: 4408200 (1983-10-01), Bradley
Digital Equipment Corp.
Fleming Michael R.
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