Diagnostic adaptor with threadless docking fixture

Details Diagnostic adaptor with threadless docking fixture Diagnostic adaptor with threadless docking fixture

2002-06-19

2004-03-23

Pert, Evan (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

Reexamination Certificate

active

06710589

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to parametric testing machines used in testing electrical characteristics of integrated circuits fabricated on a semiconductor wafer substrate. More particularly, the present invention relates to a parametric testing system diagnostic adaptor having a threadless docking fixture for removably attaching the adaptor to the test head of the system.
BACKGROUND OF THE INVENTION
A conventional method used by the semiconductor industry in the manufacturing of semiconductor integrated circuits includes the steps of fabrication, wafer sort, assembly and test, respectively. In the fabrication step, as many as several thousand dies (integrated circuits) are formed onto a semiconductor wafer. In the wafer sort step, each of the dies on the wafer is tested to determine its electrical characteristics and operability, and defective dies are distinguished from operable dies. The defective dies are often marked by an ink mark at the wafer sorting step. In the assembly step, the unmarked,operable dies are assembled into a package, and in the test step, the packaged integrated circuits are tested for operability and reliability.
At the wafer sort step, the dies are tested to establish which dies on the wafer function properly. Each die is tested to all functional product specifications for both DC and AC parameters. Four testing objectives are pursued: (1) chip functionality, in which all chip functions are tested to ensure that only fully-functional chips are assembled and packaged in subsequent steps; (2) chip sorting, in which chips are separated or sorted on the basis of their operating speed performance under various voltage and timing conditions; (3) fab yield response, which yields important information that may lead to improvements in the overall fabrication process; and (4) test coverage, in which high test coverage of the internal device nodes is achieved at the lowest possible cost. The wafer sort procedure is similar to the in-line parametric test except that every die on the wafer is tested, in many cases using the same automated test equipment (ATE). Furthermore, the wafer sort procedure is usually located in a separate facility under less stringent purity conditions than those in which the parametric test is carried out, since wafer fabrication is essentially complete.
In automated wafer handling during wafer sort, a correlation wafer is used to verify tester setup. The correlation wafer is a control wafer the functionality of which has been verified and ensures that the testing system is working properly. After indexing from the cassette to the prober, the wafers are mounted on a vacuum chuck with Z (vertical) positioning. Using software, mechanical probe needles are aligned and contacted with bond pads on the wafer to establish electrical communication between the a testing equipment and the dies on the wafer. The probes are interfaced with the ATE to perform the range of AC functional tests based on test algorithms. The type, number and order of tests are defined by the test program.
After testing, die found to be defective are labeled in a computer database to exclude the die from subsequent packaging steps. The labeling method is typically performed by placing a drop of ink on each unacceptable die. Because the ink marking process can be messy and introduce possible contaminants onto the chip, electronic wafer maps are increasingly being used to create a computer image of chip location and test results to categorize good and bad die on the wafer. At the chip assembly stations, the electronic wafer maps are downloaded into an equipment database to ensure that defective chips will not be packaged.
FIGS. 1 and 2
illustrate a conventional parametric wafer testing system, generally indicated by reference numeral
10
. The wafer testing system
10
includes a base
12
on which is mounted a wafer chuck
14
for supporting a semiconductor wafer
16
thereon and testing dies or integrated circuits on the wafer
16
. A test head
18
is connected to the base
12
by means of a hinge
20
. As illustrated in
FIG. 2
, a test face
22
on the test head
18
includes multiple pin receptacles
24
which are arranged in concentric rows and are adapted to receive pins (not illustrated) provided in electrical contact with the circuits or dies on the wafer
16
. The test head
18
is operated to conduct electrical signals between the pins of the integrated circuit package and the testing equipment (not shown) to facilitate testing of the integrated circuit package in conventional fashion.
Typically, the test head
18
requires periodic testing to ensure proper functioning of the system
10
. This is accomplished by the use of a test device
26
, which may be a relay test adapter such as an HP 16075A, a system test module such as an HP 16076A, or a test fixture adapter such as an HP 16066A. As shown in
FIG. 3A
, the test device
26
includes a test face
27
having multiple test pins
28
which are arranged in concentric rows and match the positions of the respective pin receptacles
24
of the test head
18
. Fastener openings
30
extend through the test device
26
at respective corners thereof. Accordingly, the test device
26
is removably attached to the test head
18
by inserting the test pins:
28
of the test device
26
in the respective pin receptacles
24
of the test head
18
; extending threaded fasteners
32
through respective fastener openings
30
in the test device
26
; and threadably seating the fasteners
32
in respective fastener openings
23
in the test surface
22
of the test head
18
, as illustrated in FIG.
3
. The threaded fasteners
32
mount the test device
26
against the test head
18
with a force typically equal to about 7.5 kg to maintain firm electrical contact between the test pins
28
of the test device
26
and the pin receptacles
24
of the test head
18
. After testing of the test head
18
, the test device
26
is removed from the test head
18
after unthreading the fasteners
32
from the fastener openings
23
in the test head
18
.
As the fasteners
32
are unthreaded from the fastener openings
23
, small metal particles or shavings from the fasteners
32
tend to remain in the fastener openings
23
or fall on the test face
22
of the test head
18
. This causes some of the particles or shavings to fall into the pin receptacles
24
, thereby modifying or attenuating transmission of electrical current between the test pins of the integrated circuit package (not illustrated) on a wafer
14
and the pin receptacles
24
in the test head
18
. This may render faulty the testing process for the integrated circuits on the wafer
14
.
Accordingly, a threadless docking fixture is needed to art facilitate removably mounting a test device to a test head of a parametric wafer testing system in order to prevent the metal particle contamination which is a common drawback of using conventional threaded fastener techniques for mounting the test device on the test head.
An object of the present invention is to provide a device for removably mounting a test device on a test head of a wafer testing system.
Another object of the present invention is to provide a device which is capable of removably attaching a test device on a test head of a wafer testing system without contaminating the test head.
Still another object of the present invention is to provide a threadless docking fixture for a test device used in testing a wafer testing system, which threadless docking fixture utilizes a threadless mechanism for mounting in order to prevent metal particle contamination of the test device or wafer testing system.
A still further object of the present invention is to provide a threadless docking fixture which prevents metal particle contamination of a wafer testing procedure.
Yet another object of the present invention is to provide a threadless docking fixture which is characterized by simple construction and ease of use.
A still further object of the present invention is to provide a threadless docking fi

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