Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2006-05-03
2008-12-23
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C257S777000, C385S014000, C385S015000
Reexamination Certificate
active
07468558
ABSTRACT:
Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed of a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.
REFERENCES:
patent: 4380365 (1983-04-01), Gross
patent: 5046800 (1991-09-01), Blyler, Jr. et al.
patent: 5130356 (1992-07-01), Feuerherd et al.
patent: 5302656 (1994-04-01), Kohara et al.
patent: 5359208 (1994-10-01), Katsuki et al.
patent: 5434196 (1995-07-01), Ohkawa et al.
patent: 5462995 (1995-10-01), Hosaka et al.
patent: 5581414 (1996-12-01), Snyder
patent: 5896479 (1999-04-01), Vladic
patent: 6022498 (2000-02-01), Buazza et al.
patent: 6039897 (2000-03-01), Lochhead et al.
patent: 6156394 (2000-12-01), Schultz Yamasaki et al.
patent: 6206673 (2001-03-01), Lipscomb et al.
patent: 6253004 (2001-06-01), Lee et al.
patent: 6259567 (2001-07-01), Brown et al.
patent: 6262414 (2001-07-01), Mitsuhashi
patent: 6272275 (2001-08-01), Cortright et al.
patent: 6281508 (2001-08-01), Lee et al.
patent: 6432328 (2002-08-01), Hamanaka et al.
patent: 6500603 (2002-12-01), Shioda
patent: 7099525 (2006-08-01), Bakir et al.
patent: 7135777 (2006-11-01), Bakir et al.
patent: 2006/0104566 (2006-05-01), Bakir et al.
Chen, et al.: Fully Embedded Board-Level Guided-Wave Optoelectronic Interconnects; Jun. 2000; Proceedings of IEEE, vol. 88, No. 6; pp. 780-793.
Wiesmann, et al.; Singlemode Polymer Waveguides for Optical Backplanes; Dec. 5, 1996; Electronics Letters, vol. 32, No. 25; pp. 2329-2330.
Barry, et al.; Highly Efficient Coupling Between Single-Mode Fiber and Polymer Optical Waveguides; Aug. 1997; IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, vol. 20, No. 3; pp. 225-228.
Lee, et al.; Fabrication of Polymeric Large-Core Waveguides for Optical Interconnects Using a Rubber Molding Process; Jan. 2000; IEEE Photonics Technology Letters, vol. 12, No. 1; pp. 62-64.
Schmeider, et al.; Electro-Optical Printed Circuit Board (EOPCB); 2000 Electronic Components and Technoogy Conference; pp. 749-753.
Mederer, et al.; 3Gb/s Data Transmission With GaAs VCSELs Over PCB Integrated Polymer Waveguides; Sep. 2001; IEEE Photonics Technology Letters, vol. 13, No. 9; pp. 1032-1034.
Schröder, et al.; Polymer Optical Interconnects for PCB; 2001; Session 13: Photonic Polymers II; pp. 337-343.
Glukh, et al.; High performance Polymeric Materials for Waveguide Applications; Aug. 2000; SPIE—The International Society for Optical Engineering, inear, Nonlinear, and Power Limiting Organics, San Diego, vol. 4106; pp. 1-11.
Liu, et al.; Plastic VCSEL Array Packaging and High Density Polymer Waveguides for Board and Backplane Optical Interconnect; 1998; Electronic Components and Technology Conference; pp. 999-1005.
Bakir, et al.; Sea of Dual Mode Polymer Pilliar I/O Interconnections for Gigascale Integration; 2003; IEEE International Solid State Circuits Conference; 8 pages.
Beuret, et al.; Microfabrication of 3D Multidirectional Inclined Structure by UV lithography and Electroplating; Micro Electro Mechanical Systems, 1994, MEMS'94, Proceedings, IEEE Workshop on Jan. 25-28, 1994; pp. 81-85.
Wang, et al.; Studies on A Novel Flip-Chip Interconnect Structure-Pillar Bump; Electronic Components and Technology Conference, 2001, Proceedings, 51st, May 1, Jun. 2001; pp. 945-949.
Bakir, et al.; Sea of Polymer Pillars: Dual-Mode Electrical Optical Input/Output Interconnections; in Proc. of Int. Interconnect Technology Conference; pp. 77-79; 2003.
Bakir, et al.; Sea of Polymer Pillars: Compliant Wafer-Level Electrical-Optical Chip I/O Interconnections; IEEE Photonics Technology Letters, vol. 15, No. 11, Nov. 2003; pp. 1567-1569.
Bakir, et al.; Optical Transmission of Polymer Pillars for Chip I/O Optical Interconnections; IEEE Photonics Technology Letters, vol. 16, No. 1, Jan. 2004; pp. 117-119.
Chandrasekhar, et al.; Modeling and Characterization of the Polymer Stud Grid Array (PSGA) Package; Electrical, Thermal and Thermo-Mechanical Qualification; IEEE Transactions on Electronics Packaging Manufacturing, vol. 26, No. 1, Jan. 2003; pp. 54-67.
Bakir, et al.; Optical Transmission of Polymer Pillars for Chip I/O Optical Interconnections; IEEE Photonics Technology Letters; vol. 16, No. 1, Jan. 2004; pp. 117-119.
Bakir, et al.; Sea of Polymer Pillars: Compliant Wafer-Level Electrical-Optical Chip I/O Interconnections; IEEE Photonics Technology Letters, vol. 15, No. 11, Nov. 2003; pp. 1567-1569.
Bakir, et al.; Sea of Polymer Pillars Electrical and Optical Chip I/O Interconnections for Gigascale Intergration; IEEE Transactions on Electron Devices; vol. 51, No. 7; Jul. 2004; pp. 1069-1077.
Bakir, et al.; Integration of Optical Polymer Pillars Chip I/O Interconnections with Si MSM Photodetectors; IEEE Transactions on Electron Devices; vol. 51, No. 7; Jul. 2004; pp. 1084-1090.
W. Wayt Gibbs; Computing at the Speed of Light; Scientific American; Nov. 2004; pp. 81-87.
John Baliga; Polymer Pillars for Optical and Electrical Signals; Semiconductor International; Dec. 2004; p. 36.
Richard Ball; ISSCC: Polymer Pillars Used to Connect Die; Electronics Weekly Archive; Feb. 2003.
Ron Wilson; Session Examines Novel Semiconductor Devices; EE Times; Feb. 12, 2003; URL: http://eetimes.com/article/showArticle.jhtml?articleID=18308034.
Bakir Muhannad S.
Martin Kevin P.
Meindl James D.
Georgia Tech Research Corporation
Thomas Kayden Horstemeyer & Risley LLP
Tran Thien F
LandOfFree
Devices having compliant wafer-level input/output... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Devices having compliant wafer-level input/output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Devices having compliant wafer-level input/output... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4020601