Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Bidirectional rectifier with control electrode
Reexamination Certificate
1998-03-09
2001-08-14
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Bidirectional rectifier with control electrode
C257S156000, C257S578000
Reexamination Certificate
active
06274892
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductors, and, more particularly, to a method of fabricating power semiconductor devices, and the devices produced by the method.
BACKGROUND OF THE INVENTION
Electronic power switching devices are widely used in many applications, such as, for example, motor controls, inverters, line switches, pulse circuits, and other power switching applications. A silicon controlled rectifier (SCR) or thyristor is a bistable semiconductor switching device formed from four layers of silicon. One type of power switching device, the MOS controlled thyristor (MCT) is especially suited for resonant (zero voltage or zero current switching) applications. The MCT has a forward voltage drop much like the SCR, and therefore enjoys greatly reduced conduction power loss. The MCT allows the control of high power circuits with very small amounts of input energy—a feature common to SCRs as well. In an MCT, turn-off is accomplished by turning on a highly interdigitated off-FET to short out one or both of the emitter-base junctions of a thyristor.
Another advantageous power switching device is the insulated gate bipolar transistor (IGBT) which is designed for high voltage, low on-dissipation applications, such as switching regulators and motor drivers. The IGBT can be operated from low power integrated circuits. The IGBT is also an insulated gate, field controlled switching device like the MCT. Available MCTs and IGBTs are useful at high switching frequency than is generally practice with power Darlington transistors, for example. In addition, both may be operated with junction temperatures of 150° C. and above, and operate in switching circuits having 600 volts or higher switch ratings.
One approach to fabricating power switching devices involves direct semiconductor-semiconductor wafer bonding. The wafer bonding has been for the purpose of replacing a thick, e.g. 100 &mgr;m epitaxial layer growth. For this bonding application, high temperature bonding anneals at temperatures of greater than about 1100° C. are typically used to remove microvoids and bubbles. Both hydrophobic and hydrophilic bonding has been used.
Recently there has been increasing interest in the possibility of fabricating switching power devices with MOSFET current control devices on both the front side and back side of the power device to achieve faster turnoff of the device such as disclosed in U.S. Pat. No. 4,977,438 to Abbas. The conventional approach for fabricating double-sided MOSFET controlled power devices is to perform processing and photosteps on both sides of the wafer. This approach required critical control of thermal budgets, has approximately a factor of two increase in fabrication steps, and increases the possibility of yield loss due to scratches, etc.
U.S. Pat. No. 5,541,122 to Tu et al., for example, discloses a fabrication method for IGBT wherein two wafers are bonded together, and annealed at a temperature in a range of 800 to 1100° C. An N-type wafer is doped N+ at a surface thereof and is bonded to a P+ wafer to define an N+ buffer region for the IGBT. Thereafter, a gate is formed on the upper surface and various diffusions are also made adjacent the gate to define an emitter/collector encircling the gate. An emitter contact is formed on the diffusions and a collector contact is deposited on the lower surface of the wafer using conventional techniques.
Unfortunately, the relatively high temperature annealing and subsequent device processing steps may adversely affect the doping profile of the buffer layer. Accordingly, the turnoff speed may be reduced. In addition, the double-sided processing after annealing requires a relatively large number of process steps, and the substrates are subject to mechanical damage which may reduce yields.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide semiconductor devices with enhanced characteristics and properties, and which may be readily manufactured.
These and other objects, advantages and features in accordance with the present invention are provided by a first embodiment of a semiconductor device comprising a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. In addition, the buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The negative temperature coefficient for current gain provides reduces thermal run away and provides better short circuit protection for the device.
The base may have a first conductivity type dopant in a concentration less than the concentration of first conductivity type dopant in the buffer. In addition, the buffer may have a thickness less than about 10 microns, and more preferably in a range of about 200 to 500 nanometers. The dopant concentration of the buffer is preferably greater than about 3×10
18
cm
−3
for one embodiment, and greater than about 1×10
17
cm
−3
for another.
At least one of the base and the emitter may comprise silicon, and the buffer may also comprise silicon in one embodiment. In another embodiment the buffer may comprise germanium.
The semiconductor device may be formed according to low temperature bonding as described in detail below. Accordingly, in one embodiment the device further includes a bonded interface between the emitter and the buffer. The bonded interface may also be between the buffer and the base. The bonded interface is preferably substantially devoid of oxide.
In a variation of the device, the emitter comprises an epitaxial portion adjacent the buffer and a second portion opposite the epitaxial portion. In addition, the semiconductor device may include a MOSFET current control device, or other current control device, formed in at least one of the first and second portions.
Yet another device in accordance with the present invention includes a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions. The localized lifetime killing portion may comprise a plurality of laterally confined and laterally spaced apart lifetime killing regions. A bonded interface may be between the localized lifetime killing portion and either the first or second portions. The interface may be substantially devoid of oxide. The lifetime killing regions are preferably vertically spaced from the bonded interface by a predetermined distance, such as about 10 microns.
Each of the lifetime killing regions may comprise at least one of defects and implanted impurities. In addition, the regions may in the form of circles of about 2-20 &mgr;m in diameter and spaced about 5-20 &mgr;m apart. Alternately, each of the lifetime killing regions may comprise a strip region having a width of about 2 to 20 microns. The adjacent strip regions may be spaced about 5 to 20 microns apart.
Another aspect of the invention relates to devices including one or more PN junctions. The semiconductor device may comprise a first laterally extending portion having a first conductivity type dopant; a second laterally extending portion on the first portion, the second portion also having the first conductivity type dopant; and at least one doped region of second conductivity type formed in the first portion adjacent an interface between the first and second portions and defining at least one PN junction. Moreover, a conductive layer may be positioned between the at least one doped region and the second portion to lower a resistance of the PN junction. The conductive layer may be a metal or silicide, for example.
One implementation of the PN junction may be to provide junctions spac
Hobart Karl
Kub Francis J.
Neilson John
Temple Victor
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chaudhuri Olik
Ha Nathan W.
Intersil America's Inc.
LandOfFree
Devices formable by low temperature direct bonding does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Devices formable by low temperature direct bonding, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Devices formable by low temperature direct bonding will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2465698